AMD AMD-K6-2/500AFX Data Sheet - Page 256
Debug, Debug Registers, Make use of the Flush/Invalidate Register PFIR
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 system logic, including the execution of writeback cycles when a modified cache line is hit. While the L1 is inhibited, the processor continues to drive the PCD output signal appropriately, which system logic can use to control external caching. In order to completely disable the L1 cache so no valid lines exist in the cache, the Cache Inhibit bit must be set to 1 and the cache must be flushed in one of the following ways: s Asserting the FLUSH# input signal s Executing the WBINVD instruction s Executing the INVD instruction (modified cache lines are not written back to memory) s Make use of the Page Flush/Invalidate Register (PFIR) (AMD-K6-2/[F:8] only)(see "PFIR" on page 195) 11.5 Debug Debug Registers The AMD-K6-2 processor implements the standard x86 debug functions, registers, and exceptions. In addition, the processor supports the I/O breakpoint debug extension. The debug feature assists programmers and system designers during software execution tracing by generating exceptions when one or more events occur during processor execution. The exception handler, or debugger, can be written to perform various tasks, such as displaying the conditions that caused the breakpoint to occur, displaying and modifying register or memory contents, or single-stepping through program execution. The following sections describe the debug registers and the various types of breakpoints and exceptions that the processor supports. Figures 87 through 90 show the 32-bit debug registers supported by the processor. 236 Test and Debug Chapter 11