AMD AMD-K6-2/500AFX Data Sheet - Page 120
EADS# (External Address Strobe
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.20 Summary Sampled EADS# (External Address Strobe) Input System logic asserts EADS # during a cache inquire cycle to indicate that the address bus contains a valid address. EADS# can only be driven after the system logic has taken control of the address bus by asserting AHOLD or BOFF# or by receiving HLDA. The processor responds to the sampling of EADS# and the address bus by driving HIT#, which indicates if the inquired cache line exists in the processor's cache, and HITM#, which indicates if it is in the modified state. If AHOLD or BOFF# is asserted by the system logic in order to execute a cache inquire cycle, the processor begins sampling EADS # two clock edges after AHOLD or BOFF # is sampled asserted. If the system logic asserts HOLD in order to execute a cache inquire cycle, the processor begins sampling EADS# two clock edges after the clock edge HLDA is asserted by the processor. EADS # is ignored during the following conditions: s One clock edge after the clock edge on which EADS# is sampled asserted s Two clock edges after the clock edge on which ADS# is asserted s When the processor is driving the address bus s When the processor asserts HITM# 100 Signal Descriptions Chapter 4