AMD AMD-K6-2/500AFX Data Sheet - Page 267
Exit Stop Clock State, Clock Control, AMD-K6, 2 Processor Data Sheet
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Exit Stop Clock State The AMD-K6-2 processor returns to the Stop Grant state from the Stop Clock state after the CLK signal is started and the internal PLL has stabilized. PLL stabilization is achieved after the CLK signal has been running within its specification for a minimum of 1.0 ms. The frequency of CLK when exiting the Stop Clock state can be different than the frequency of CLK when entering the Stop Clock state. The state of the BF[2:0] signals when exiting the Stop Clock state is ignored because the BF[2:0] signals are only sampled during the falling transition of RESET. Chapter 12 Clock Control 247
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Chapter 12
Clock Control
247
21850J/0—February 2000
AMD-K6
®
-2 Processor Data Sheet
Preliminary Information
Exit Stop Clock State
The AMD-K6-2 processor returns to the Stop Grant state from
the Stop Clock state after the CLK signal is started and the
internal PLL has stabilized. PLL stabilization is achieved after
the CLK signal has been running within its specification for a
minimum of 1.0 ms.
The frequency of CLK when exiting the Stop Clock state can be
different than the frequency of CLK when entering the Stop
Clock state.
The state of the BF[2:0] signals when exiting the Stop Clock
state is ignored because the BF[2:0] signals are only sampled
during the falling transition of RESET.