AMD AMD-K6-2/500AFX Data Sheet - Page 146
Table 24., Bus Cycle Definition, Special Cycles, Bus Cycle Initiated, Generated by the Processor
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 24. Bus Cycle Definition Bus Cycle Initiated Code Read, Instruction Cache Line Fill Code Read, Noncacheable Code Read, Noncacheable Encoding for Special Cycle Interrupt Acknowledge I/O Read I/O Write Memory Read, Data Cache Line Fill Memory Read, Noncacheable Memory Read, Noncacheable Memory Write, Data Cache Writeback Memory Write, Noncacheable Note: x means "don't care" Generated by the Processor Generated by the System M/IO# 1 1 1 0 0 0 0 1 1 1 1 1 D/C# 0 0 0 0 0 1 1 1 1 1 1 1 W/R# 0 0 0 1 0 0 1 0 0 0 1 1 CACHE# 0 1 x 1 1 1 1 0 1 x 0 1 KEN# 0 x 1 x x x x 0 x 1 x x A4 BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# M/IO# D/C# W/R# CACHE# KEN# Table 25. Special Cycles Special Cycle Stop Grant 1111110110011x Flush Acknowledge (FLUSH# sampled asserted) 0 1 1 1 0 1 1 1 1 0 0 1 1 x Writeback (WBINVD instruction) 0111101110011x Halt 0111110110011x Flush (INVD, WBINVD instruction) 0111111010011x Shutdown 0111111100011x Note: x means "don't care" 126 Signal Descriptions Chapter 4