AMD AMD-K6-2/500AFX Data Sheet - Page 229
Multimedia and 3DNow!™ Execution Units
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 9.2 Multimedia and 3DNow!™ Execution Units The multimedia and 3DNow! execution units of the AMD-K6-2 processor are designed to accelerate the performance of software written using the industry-standard MMX instructions and the new 3DNow! instructions. Applications that can take advantage of the MMX and 3DNow! instructions include graphics, video and audio compression and decompression, speech recognition, and telephony applications. The multimedia execution unit can execute MMX instructions in a single processor clock. All MMX and 3DNow! arithmetic instructions are pipelined for higher performance. To increase performance, the processor is designed to simultaneously decode all MMX and 3DNow! instructions with most other instructions. For more information on MMX instructions, see the AMD-K6® Processor Multimedia Technology Manual, order# 20726. For more information on 3DNow! instructions, see the 3DNow!™ Technology Manual, order# 21928. 9.3 Floating-Point and MMX™/3DNow!™ Instruction Compatibility Registers Exceptions FERR# and IGNNE# The eight 64-bit MMX registers (which are also utilized by 3DNow! instructions) are mapped on the floating-point stack. This enables backward compatibility with all existing software. For example, the register saving event that is performed by operating systems during task switching requires no changes to the operating system. The same support provided in an operating system's interrupt 7 handler (Device Not Available) for saving and restoring the floating-point registers also supports saving and restoring the MMX registers. There are no new exceptions defined for supporting the MMX and 3DNow! instructions. All exceptions that occur while decoding or executing an MMX or 3DNow! instruction are handled in existing exception handlers without modification. MMX instructions and 3DNow! instructions do not generate f l o a t i n g -p o i n t e x c e p t i o n s . H oweve r, i f a n u n m a s ke d floating-point exception is pending, the processor asserts FERR# at the instruction boundary of the next floating-point Chapter 9 Floating-Point and Multimedia Execution Units 209
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