AMD AMD-K6-2/500AFX Data Sheet - Page 204
CacheLine Fills, MTRRs in the UWCCR MSR see Memory Type Range
View all AMD AMD-K6-2/500AFX manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 204 highlights
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 For the system logic to flush the cache, the processor must sample FLUSH# asserted. In this method, the processor writes back any data cache lines that are in the modified state, invalidates all lines in the instruction and data caches, and then executes a flush acknowledge special cycle (See Table 25 on page 126). The second method for flushing the caches is for software to execute the WBINVD instruction which causes all modified lines to first be written back to memory, then marks all cache lines as invalid. Alternatively, if writing modified lines back to memory is not necessary, the INVD instruction can be used to invalidate all cache lines. The third and final method for flushing the caches is to make use of the Page Flush/Invalidate Register (PFIR), which allows cache invalidation and optional flushing of a specific 4-Kbyte page from the linear address space. The PFIR is only supported on the AMD-K6-2 processor Model 8/[F:8] (see "PFIR" on page 195). Unlike the previous two methods of flushing the caches, this particular method requires the software to be aware of which specific pages must be flushed and invalidated. 7.5 Cache-Line Fills The processor performs a cache-line fill for any area of system memory defined as cacheable. If an area of system memory is not explicitly defined as uncacheable by the software or system logic, or implicitly treated as uncacheable by the processor, then the memory access is assumed to be cacheable. Software can prevent caching of certain pages by setting the PCD bit in the PDE or PTE. Additionally, for the AMD-K6-2 processor Model 8/[F:8], software can define regions of memory as uncacheable or write combinable by programming the MTRRs in the UWCCR MSR (see "Memory Type Range Registers" on page 203). Write-combinable memory is defined as uncacheable. The system logic also has control of the cacheability of bus cycles. If it determines the address is not cacheable, system logic negates the KEN# signal when asserting the first BRDY# or NA# of a cycle. 184 Cache Organization Chapter 7