AMD AMD-K6-2/500AFX Data Sheet - Page 201
Cache Operation, See Write Allocate
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet each instruction byte. The predecode bits indicate the number of bytes to the start of the next x86 instruction. The predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding. The predecode bits use memory separate from the 32-Kbyte instruction cache. The predecode bits are stored in an extended instruction cache alongside each x86 instruction byte as shown in Figure 78. 7.3 Cache Operation The operating modes for the caches are configured by software using the not writethrough (NW) and cache disable (CD) bits of control register 0 (CR0 bits 29 and 30, respectively). These bits are used in all operating modes. When the CD and NW bits are both set to 0, the cache is fully enabled. This is the standard operating mode for the cache. If a read miss occurs when the processor reads from the cache, a line fill (32-byte burst read) on the system bus occurs in order to fetch the cache line. Write hits to the cache are updated, while write misses and writes to shared lines cause external memory updates. Refer to Table 36 on page 193 for a summary of cache read and write cycles and the effect of these operations on the cache MESI state. Note: A write allocate operation can modify the behavior of write misses to the cache. See "Write Allocate" on page 186. When CD is set to 0 and NW is set to 1, an invalid mode of operation exists that causes a general protection fault to occur. When CD is set to 1 (disabled) and NW is set to 0, the cache fill mechanism is disabled but the contents of the cache are still valid. The processor reads from the cache and, if a read miss occurs, no line fill takes place. Write hits to the cache are updated, while write misses and writes to shared lines cause external memory updates. If PWT is driven Low and WB/WT# is sampled High, a write hit to a shared line changes the cacheline state to exclusive. When the CD and NW bits are both set to 1, the cache is fully disabled. Even though the cache is disabled, the contents are not necessarily invalid. The processor reads from the cache and, if a read miss occurs, no line fill takes place. If a write hit Chapter 7 Cache Organization 181