AMD AMD-K6-2/500AFX Data Sheet - Page 194
RESET Requirements, 6.3 State of Processor After RESET, Output Signals, Registers
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 6.2 RESET Requirements During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification. (See "CLK Switching Characteristics" on page 267 for clock specifications. See "Electrical Data" on page 253 for VCC specifications.) During a warm reset while CLK and VCC are within specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. 6.3 State of Processor After RESET Output Signals Table 31 shows the state of all processor outputs and bidirectional signals immediately after RESET is sampled asserted. Table 31. Output Signal State After RESET Signal A[31:3], AP ADS#, ADSC# APCHK# BE[7:0]# BREQ CACHE# D/C# D[63:0], DP[7:0] FERR# HIT# HITM# HLDA State Floating High High Floating Low High Low Floating High High High Low Signal LOCK# M/IO# PCD PCHK# PWT SCYC SMIACT# TDO VCC2DET VCC2H/L# W/R# - State High Low Low High Low Low High Floating Low Low Low - Registers Table 32 on page 175 shows the state of all architecture registers and Model-Specific Registers (MSRs) after the processor has completed its initialization due to the recognition of the assertion of RESET. 174 Power-on Configuration and Initialization Chapter 6