AMD AMD-K6-2/500AFX Data Sheet - Page 210
CD Bit of CR0, PCD Signal, UC or WC, Write to a Cacheable CCR,
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 1) CD Bit of CR0 2) PCD Signal 3) CI Bit of TR12 4) UC or WC 5) Write to Cacheable Page (CCR) 6) Write to a Sector 7) Less Than Limit (WAELIM) 8) Between 640 Kbytes and 1 Mbyte 9) Between 15-16 Mbytes 10) Write Allocate Enable 15-16 Mbyte (WAE15M) Perform Write Allocate Figure 81. Write Allocate Logic Mechanisms and Conditions The following list describes the corresponding items in Figure 81: 1. CD Bit of CR0-When the cache disable (CD) bit within control register 0 (CR0) is set to 1, the cache fill mechanism for both reads and writes is disabled and write allocate does not occur. 2. PCD Signal-When the PCD (page cache disable) signal is driven High, caching for that page is disabled, even if KEN# is sampled asserted, and write allocate does not occur. 3. CI Bit of TR12-When the cache inhibit bit of Test Register 12 is set to 1, L1 cache fills are disabled and write allocate does not occur. 4. UC or WC-If a pending write cycle addresses a region of memory defined as write combinable or uncacheable by an MTRR, write allocates are not performed in that region. MTRRs are only supported in the AMD-K6-2 processor Model 8/[F:8]. For all other steppings, treat this condition as equal to 0. 5. Write to a Cacheable Page (CCR)-A write allocate is performed if the processor knows that a page is cacheable. The CCR is used to store the page address of the last cache fill for a read miss. See "Write to a Cacheable Page" on page 186 for a detailed description of this condition. 190 Cache Organization Chapter 7