AMD AMD-K6-2/500AFX Data Sheet - Page 240
Exceptions, Interrupts, and Debug in SMM
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 10.9 220 The processor initializes the I/O trap restart slot to 0000h upon entry into SMM. If SMM was entered due to a trapped I/O instruction, the processor indicates the validity of the I/O instruction by setting or clearing bit 1 of the I/O trap dword at offset FFA4h in the SMM state-save area. The SMM service routine should test bit 1 of the I/O trap dword to determine if a valid I/O instruction was being executed when entering SMM and before writing the I/O trap restart slot. If the I/O instruction is valid, the SMM service routine can safely rewrite the I/O trap restart slot with the value 00FFh, which causes the processor to re-execute t he trapped I/O instruction w hen the RSM instruction is executed. If the I/O instruction is invalid, writing the I/O trap restart slot has undefined results. If a second SMI# is asserted and a valid I/O instruction was trapped by the first SMM handler, the processor services the second SMI# prior to re-executing the trapped I/O instruction. The second entry into SMM never has bit 1 of the I/O trap dword set, and the second SMM service routine must not rewrite the I/O trap restart slot. During a simultaneous SMI# I/O instruction trap and debug breakpoint trap, the AMD-K6-2 processor first responds to the SMI# and postpones recognizing the debug exception until after returning from SMM via the RSM instruction. If the debug registers DR3-DR0 are used while in SMM, they must be saved and restored by the SMM handler. The processor automatically saves and restores DR7-DR6. If the I/O trap restart slot in the SMM state-save area contains the value 00FFh when the RSM instruction is executed, the debug trap does not occur until after the I/O instruction is re-executed. Exceptions, Interrupts, and Debug in SMM During an SMI# I/O trap, the exception/interrupt priority of the AMD-K6-2 processor changes from its normal priority. The normal priority places the debug traps at a priority higher than the sampling of the FLUSH# or SMI# signals. However, during an SMI# I/O trap, the sampling of the FLUSH# or SMI# signals takes precedence over debug traps. The processor recognizes the assertion of NMI within SMM immediately after the completion of an IRET instruction. Once NMI is recognized within SMM, NMI recognition remains enabled until SMM is exited, at which point NMI masking is restored to the state it was in before entering SMM. System Management Mode (SMM) Chapter 10