AMD AMD-K6-2/500AFX Data Sheet - Page 28
Internal Architecture, AMD-K6, 2 Processor Data Sheet, EAX, EBX, ECX, EDX, EBP, ESP, ESI
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Short and long decodes are processed completely within the decoders. Vector decodes are started by the decoders and then completed by fetched sequences from an on-chip ROM. After decoding, the RISC86 operations are delivered to the scheduler for dispatching to the executions units. Scheduler/Instruction Control Unit. The centraliz ed scheduler or buffer is managed by the Instruction Control Unit (ICU). The ICU buffers and manages up to 24 RISC86 operations at a time. This equals from 6 to 12 x86 instructions. This buffer size (24) is perfectly matched to the processor's six-stage RISC86 pipeline and four RISC86-operations decode rate. The scheduler accepts as many as four RISC86 operations at a time from the decoders and retires up to four RISC86 operations per clock cycle. The ICU is capable of simultaneously issuing up to six RISC86 operations at a time to the execution units. This consists of the following types of operations: s Memory load operation s Memory store operation s Complex integer, MMX or 3DNow! register operation s Simple integer, MMX or 3DNow! register operation s Floating-point register operation s Branch condition evaluation Registers. When managing the 24 RISC86 operations, the ICU uses 69 physical registers contained within the RISC86 microarchitecture. 48 of the physical registers are located in a general register file and are grouped as 24 committed or architectural registers plus 24 rename registers. The 24 architectural registers consist of 16 scratch registers and 8 registers that correspond to the x86 general-purpose registers- EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. There is an analogous set of registers specifically for MMX and 3DNow! operations. There are 9 MMX/3DNow! committed or architectural registers plus 12 MMX/3DNow! rename registers. The 9 architectural registers consist of one scratch register and 8 registers that correspond to the MMX registers (mm0-mm7), as shown in Figure 17 on page 29. Branch Logic. The AMD-K6-2 processor is designed with highly sophisticated dynamic branch logic consisting of the following: s Branch history/Prediction table s Branch target cache s Return address stack 8 Internal Architecture Chapter 2