AMD AMD-K6-2/500AFX Data Sheet - Page 184
Special Bus Cycles, Cycle
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 5.6 Special Bus Cycles The AMD-K6-2 processor drives special bus cycles that include stop grant, flush acknowledge, cache writeback invalidation, halt, cache invalidation, and shutdown cycles. During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1. BE[7:0]# and A[31:3] are driven to differentiate among the special cycles, as shown in Table 30. The system logic must return BRDY# in response to all processor special cycles. Table 30. Encodings For Special Bus Cycles BE[7:0]# A[4:3]* FBh 10b EFh 00b F7h 00b FBh 00b FDh 00b FEh 00b Note: * A[31:5] = 0 Special Bus Cycle Cause Stop Grant STPCLK# sampled asserted Flush Acknowledge FLUSH# sampled asserted Writeback WBINVD instruction Halt HLT instruction Flush INVD,WBINVD instruction Shutdown Triple fault Basic Special Bus Cycle Figure 72 shows a basic special bus cycle. The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the same clock edge that it asserts ADS#. In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h, which indicates that the special cycle is a halt special cycle (See Table 30). A halt special cycle is generated after the processor executes the HLT instruction. If the processor samples FLUSH# asserted, it writes back any data cache lines that are in the modified state and invalidates all lines in the instruction and data cache. The processor then drives a flush acknowledge special cycle. If the processor executes a WBINVD instruction, it drives a writeback special cycle after the processor completes invalidating and writing back the cache lines. 164 Bus Cycles Chapter 5