AMD AMD-K6-2/500AFX Data Sheet - Page 123
FLUSH# (Cache Flush
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.23 Summary Sampled FLUSH# (Cache Flush) Input In response to sampling FLUSH# asserted, the processor writes back any data cache lines that are in the modified state, invalidates all lines in the instruction and data caches, and then executes a flush acknowledge special cycle. See Table 25 on page 126 for the bus definition of special cycles. In addition, FLUSH# is sampled when RESET is negated to determine if the processor enters the Tri-State Test mode. If FLUSH # is 0 during the falling transition of RESET, the processor enters the Tri-State Test mode instead of performing the normal RESET functions. FLUSH # is sampled and latched as a falling edge-sensitive signal. During normal operation (not RESET), FLUSH # is sampled on every clock edge but is not recognized until the next instruction boundary. If FLUSH# is asserted synchronously, it can be asserted for a minimum of one clock. If FLUSH # is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. FLUSH# is also sampled during the falling transition of RESET. If RESET and FLUSH# are driven synchronously, FLUSH# is sampled on the clock edge prior to the clock edge on which RESET is sampled negated. If RESET is driven asynchronously, the minimum setup and hold time for FLUSH#, relative to the negation of RESET, is two clocks. Chapter 4 Signal Descriptions 103