AMD AMD-K6-2/500AFX Data Sheet - Page 266
Stop Grant Inquire State, 12.4 Stop Clock State, Enter Stop Grant, Inquire State, State
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or SMI# are sampled asserted in the Stop Grant state, the processor latches the edge-sensitive signals (INIT, FLUSH#, NMI, and SMI#), but otherwise does not exit the Stop Grant state to service the interrupt. When the processor returns to the Normal state due to sampling STPCLK# negated, any pending interrupts are recognized after returning to the Normal state. To ensure their recognition, all of the normal requirements for these input signals apply within the Stop Grant state. If RESET is sampled asserted in the Stop Grant state, the processor immediately returns to the Normal state and the reset process begins. 12.3 Stop Grant Inquire State Enter Stop Grant Inquire State Exit Stop Grant Inquire State The Stop Grant Inquire state is entered from the Stop Grant state or the Halt state when EADS# is sampled asserted during an inquire cycle initiated by the system logic. The AMD-K6-2 processor responds to an inquire cycle in the same manner as in the Normal state by driving HIT# and HITM#. If the inquire cycle hits a modified data cache line, the processor performs a writeback cycle. Following the completion of any writeback, the processor returns to the state from which it entered the Stop Grant Inquire state. 12.4 Stop Clock State Enter Stop Clock State If the CLK signal is stopped while the AMD-K6-2 processor is in the Stop Grant state, the processor enters the Stop Clock state. Because all internal clocks and the PLL are not running in the Stop Clock state, the Stop Clock state represents the minimum-power state of all clock control states. The CLK signal must be held Low while it is stopped. The Stop Clock state cannot be entered from the Halt state. INTR is the only input signal that is allowed to change states while the processor is in the Stop Clock state. However, INTR is not sampled until the processor returns to the Stop Grant state. All other input signals must remain unchanged in the Stop Clock state. 246 Clock Control Chapter 12