AMD AMD-K6-2/500AFX Data Sheet - Page 263
Clock Control, Normal State, Halt State, Stop Grant State, Stop Grant Inquire State
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 12 Clock Control The AMD-K6-2 processor supports five modes of clock control. The processor can transition between these modes to maximize performance, to minimize power dissipation, or to provide a balance between performance and power. (See "Power Dissipation" on page 257 for the maximum power dissipation of the AMD-K6-2 processor within the normal and reduced-power states.) The five clock-control states supported are as follows: s Normal State: The processor is running in Real Mode, Virtual-8086 Mode, Protected Mode, or System Management Mode (SMM). In this state, all clocks are running-including the external bus clock CLK and the internal processor clock-and the full features and functions of the processor are available. s Halt State: This low-power state is entered following the successful execution of the HLT instruction. During this state, the internal processor clock is stopped. s Stop Grant State: This low-power state is entered following the recognition of the assertion of the STPCLK# signal. During this state, the internal processor clock is stopped. s Stop Grant Inquire State: This state is entered from the Halt state and the Stop Grant state as the result of a system-initiated inquire cycle. s Stop Clock State: This low-power state is entered from the Stop Grant state when the CLK signal is stopped. The following sections describe each of the four low-power states. Figure 91 on page 248 illustrates the clock control state transitions. Chapter 12 Clock Control 243