AMD AMD-K6-2/500AFX Data Sheet - Page 287
Signal Switching Characteristics - 66 100 bus
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 16 16.1 Signal Switching Characteristics The AMD-K6-2 processor signal switching characteristics are presented in Table 61 through Table 70. Valid delay, float, setup, and hold timing specifications are listed. These specifications are provided for the system designer to determine if the timings necessary for the processor to interface with the system logic are met. Table 61 and Table 62 contain the switching characteristics of the CLK input. Table 63 through Table 66 contain the timings for the normal operation signals. Table 67 and Table 68 contain the timings for RESET and the configuration signals. Table 69 and Table 70 contain the timings for the test operation signals. All signal timings provided are: s Measured between CLK, TCK, or RESET at 1.5 V and the corresponding signal at 1.5 V-this applies to input and output signals that are switching from Low to High, or from High to Low s Based on input signals applied at a slew rate of 1 V/ns between 0 V and 3 V (rising) and 3 V to 0 V (falling) s Valid within the operating ranges given in "Operating Ranges" on page 253 s Based on a load capacitance (CL) of 0 pF CLK Switching Characteristics Table 61 and Table 62 contain the switching characteristics of the CLK input to the AMD-K6-2 processor for 100-MHz and 66-MHz bus operation, respectively, as measured at the voltage levels indicated by Figure 95 on page 269. The CLK Period Stability specifies the variance (jitter) allowed between successive periods of the CLK input measured at 1.5 V. This parameter must be considered as one of the elements of clock skew between the AMD-K6-2 processor and the system logic. Chapter 16 Signal Switching Characteristics 267