AMD AMD-K6-2/500AFX Data Sheet - Page 196
Power-on Configuration and Initialization, AMD-K6, 2 Processor Data Sheet, Table 32.
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 32. Register State After RESET (continued) Register State (hex) Notes CR0 6000_0010h 4 CR2 0000_0000h CR3 0000_0000h CR4 0000_0000h DR7 0000_0400h DR6 FFFF_0FF0h DR3 0000_0000h DR2 0000_0000h DR1 0000_0000h DR0 0000_0000h MCAR 0000_0000_0000_0000h 3 MCTR 0000_0000_0000_0000h 3 TR12 0000_0000_0000_0000h 3 TSC 0000_0000_0000_0000h 3 0000_0000_0000_0000h (Model 8/[7:0]) EFER 3 0000_0000_0000_0002h (Model 8/[F:8]) STAR 0000_0000_0000_0000h 3 WHCR 0000_0000_0000_0000h 3 UWCCR 0000_0000_0000_0000h 3, 5 PSOR 0000_0000_0000_01SBh 3, 5, 6 PFIR 0000_0000_0000_0000h 3, 5 Notes: 1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful. If EAX is non-zero, BIST failed. 2. EDX contains the AMD-K6-2 processor signature, where X indicates the processor Stepping ID. 3. The contents of these registers are preserved following the recognition of INIT. 4. The CD and NW bits of CR0 are preserved following the recognition of INIT. 5. UWCCR, PSOR, and PFIR are implemented only on AMD-K6-2 processor Model 8/[F:8]. 6. "S" represents the Stepping. "B" represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of RESET. 176 Power-on Configuration and Initialization Chapter 6