AMD AMD-K6-2/500AFX Data Sheet - Page 66
Descriptors and Gates, Table Entry PTE
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 31 12 11 10 9 8 7 6 5 4 3 2 1 0 Physical Page Base Address A P P UW V DA CW / / P L DT SR Symbol Description Bits AVL Available to Software 11-9 Reserved 8-7 D Dirty 6 A Accessed 5 PCD Page Cache Disable 4 PWT Page Writethrough 3 U/S User/Supervisor 2 W/R Write/Read 1 P Present (valid) 0 Figure 43. Page Table Entry (PTE) Descriptors and Gates There are various types of structures and registers in the x86 architecture that define, protect, and isolate code segments, data segments, task state segments, and gates. These structures are called descriptors. Figure 44 on page 47 shows the application segment descriptor format. Table 9 contains information describing the memory segment type to which the descriptor points. The application segment descriptor is used to point to either a data or code segment. Figure 45 on page 48 shows the system segment descriptor format. Table 10 contains information describing the type of segment or gate to which the descriptor points. The system segment descriptor is used to point to a task state segment, a call gate, or a local descriptor table. The AMD-K6-2 processor uses gates to transfer control between executable segments with different privilege levels. Figure 46 on page 49 shows the format of the gate descriptor types. Table 10 contains information describing the type of segment or gate to which the descriptor points. 46 Software Environment Chapter 3
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