AMD AMD-K6-2/500AFX Data Sheet - Page 161
Misaligned I/O Read and Write, Misaligned I/O Transfer, Table 28.
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Misaligned I/O Read and Write Table 28 shows the misaligned I/O read and write cycle order executed by the AMD-K6-2 processor. In Figure 60, the least-significant bytes (LSBs) are transferred first. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to transfer the most-significant bytes (MSBs) to complete the misaligned bus cycle. Table 28. Bus-Cycle Order During Misaligned I/O Transfers Type of Access I/O Read I/O Write First Cycle LSBs LSBs Second Cycle MSBs MSBs CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# SCYC D[63:0] BRDY# Misaligned I/O Read Misaligned I/O Write ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE LSB MSB LSB MSB Figure 60. Misaligned I/O Transfer Chapter 5 Bus Cycles 141