AMD AMD-K6-2/500AFX Data Sheet - Page 297

21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 66. Input Setup and Hold Timings for 66-MHz Bus Operation (continued) Symbol Parameter Description Preliminary Data Min Max Figure Comments t68 HOLD Setup Time 5.0 ns 99 t69 HOLD Hold Time 1.5 ns 99 t70 IGNNE# Setup Time 5.0 ns 99 Note 1 t71 IGNNE# Hold Time 1.0 ns 99 Note 1 t72 INIT Setup Time 5.0 ns 99 Note 2 t73 INIT Hold Time 1.0 ns 99 Note 2 t74 INTR Setup Time 5.0 ns 99 Note 1 t75 INTR Hold Time 1.0 ns 99 Note 1 t76 INV Setup Time 5.0 ns 99 t77 INV Hold Time 1.0 ns 99 t78 KEN# Setup Time 5.0 ns 99 t79 KEN# Hold Time 1.0 ns 99 t80 NA# Setup Time 4.5 ns 99 t81 NA# Hold Time 1.0 ns 99 t82 NMI Setup Time 5.0 ns 99 Note 2 t83 NMI Hold Time 1.0 ns 99 Note 2 t84 SMI# Setup Time 5.0 ns 99 Note 2 t85 SMI# Hold Time 1.0 ns 99 Note 2 t86 STPCLK# Setup Time 5.0 ns 99 Note 1 t87 STPCLK# Hold Time 1.0 ns 99 Note 1 t88 WB/WT# Setup Time 4.5 ns 99 t89 WB/WT# Hold Time 1.0 ns 99 Notes: 1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. Chapter 16 Signal Switching Characteristics 277