AMD AMD-K6-2/500AFX Data Sheet - Page 202
Cache Organization, AMD-K6, 2 Processor Data Sheet, Entry PDE
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 occurs, the cache is updated but an external memory update does not occur. If a data line is in the exclusive state during a write hit, the cache-line state is changed to modified. Cache lines in the shared state remain in the shared state after a write hit. Write misses access external memory directly. The operating system can control the cacheability of a page. The paging mechanism is controlled by CR3, the Page Directory Entry (PDE), and the Page Table Entry (PTE). Within CR3, PDE, and PTE are Page Cache Disable (PCD) and Page Writethrough (PWT) bits. The values of the PCD and PWT bits used in Table 33 and Table 34 are taken from either the PTE or PDE. For more information see the descriptions of PCD and PWT on pages 113 and 115, respectively. Table 33 describes how the PWT signal is driven based on the values of the PWT bits and the PG bit of CR0. Table 33. PWT Signal Generation PWT Bit* PG Bit of CR0 1 1 0 1 1 0 0 0 Note: * PWT is taken from PTE or PDE PWT Signal High Low Low Low Table 34 describes how the PCD signal is driven based on the values of the CD bit of CR0, the PCD bits, and the PG bit of CR0. Table 34. PCD Signal Generation CD Bit of CR0 PCD Bit* 1 X 0 1 0 0 0 1 0 0 Note: * PCD is taken from PTE or PDE PG Bit of CR0 X 1 1 0 0 PCD Signal High High Low Low Low 182 Cache Organization Chapter 7