AMD AMD-K6-2/500AFX Data Sheet - Page 227
FloatingPoint and Multimedia Execution Units, 9.1 FloatingPoint Execution Unit
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 9 Floating-Point and Multimedia Execution Units 9.1 Floating-Point Execution Unit Handling Floating-Point Exceptions The AMD-K6-2 processor contains an IEEE 754-compatible and 854-compatible floating-point execution unit designed to accelerate the performance of software that utilizes the x86 floating-point instruction set. Floating-point software is typically written to manipulate numbers that are very large or very small, that require a high degree of precision, or that result from complex mathematical operations such as transcendentals. Applications that take advantage of floating-point operations include geometric calculations for graphics acceleration, scientific, statistical, and engineering applications, and business applications that use large amounts of high-precision data. The high-performance floating-point execution unit contains an adder unit, a multiplier unit, and a divide/square root unit. These low-latency units can execute floating-point instructions in as few as two processor clocks. To increase performance, the processor is designed to simultaneously decode most floating-point instructions with most short-decodeable instructions. See "Software Environment" on page 21 for a description of the floating-point data types, registers, and instructions. The AMD-K6-2 processor provides the following two types of exception handling for floating-point exceptions: s If the numeric error (NE) bit in CR0 is set to 1, the processor invokes the interrupt 10h handler. In this manner, the floating-point exception is completely handled by software. s If the NE bit in CR0 is set to 0, the processor requires external logic to generate an interrupt on the INTR signal in order to handle the exception. External Logic Support of Floating-Point Exceptions The processor provides the FERR# (Floating-Point Error) and IGNNE# (Ignore Numeric Error) signals to allow the external logic to generate the interrupt in a manner consistent with IBM-compatible PC/AT systems. The assertion of FERR# indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point Chapter 9 Floating-Point and Multimedia Execution Units 207