AMD AMD-K6-2/500AFX Data Sheet - Page 213
Table 36., Data Cache States for Read and Write Accesses, Cache State Before, Access
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 36. Data Cache States for Read and Write Accesses Cache State After Access Type Cache State Before Access Access Type1 MESI State8 Writeback Writethrough State invalid single read from bus invalid - Cache Read Read Miss invalid exclusive burst read from bus, fill cache2 - shared or exclusive3 exclusive writethrough or writeback3 writeback Read Hit modified - modified writeback shared - shared writethrough invalid single write to bus4 invalid - Write Miss invalid burst read from bus, fill cache, write to cache5 modified6 - Cache Write burst read from bus, fill invalid cache, write to cache, shared7 - single write to bus5 exclusive or modified write to cache modified writeback Write Hit shared write to cache, single write to bus shared or exclusive3 writethrough or writeback3 Notes: 1. Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32-byte burst read. 2. If CACHE# is driven Low and KEN# is sampled asserted. 3. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If PWT is driven High or WB/WT# is sampled Low, the line is cached in the shared (writethrough) state. 4. Assumes the write allocate conditions as specified in "Write Allocate" on page 186 are not met. 5. Assumes the write allocate conditions as specified in "Write Allocate" on page 186 are met. 6. Assumes PWT is driven Low and WB/WT# is sampled High. 7. Assumes PWT is driven High or WB/WT# is sampled Low. 8. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a particular cache line. - Not applicable or none. Chapter 7 Cache Organization 193