AMD AMD-K6-2/500AFX Data Sheet - Page 144
Table 20., Input Pin Types, Asynchronous, IGNNE, AHOLD, BF[2:0], BRDYC, Clock, RESET, FLUSH, STPCLK
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 20. Input Pin Types Name Type Note Name Type Note A20M# Asynchronous 1 IGNNE# Asynchronous 1 AHOLD Synchronous INIT Asynchronous 2 BF[2:0] Synchronous 4 INTR Asynchronous 1 BOFF# Synchronous INV Synchronous BRDY# Synchronous KEN# Synchronous BRDYC# Synchronous 7 NA# Synchronous CLK Clock NMI Asynchronous 2 EADS# Synchronous RESET Asynchronous 5, 6 EWBE# Synchronous 8 SMI# Asynchronous 2 FLUSH# Asynchronous 2, 3 STPCLK# Asynchronous 1 HOLD Synchronous WB/WT# Synchronous Notes: 1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 3. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which RESET is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the negation of RESET. 4. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET. 5. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification before it is negated. 6. During a warm reset, while CLK and VCC are within their specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. 7. BRDYC# is also sampled during the falling transition of RESET. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET. If asserted asynchronously, BRDYC# must meet a minimum setup and hold time of two clocks relative to the negation of RESET. 8. On the AMD-K6-2 processor Model 8/[F:8], if EFER[3] is set to 1, then EWBE# is ignored by the processor. 124 Signal Descriptions Chapter 4