AMD AMD-K6-2/500AFX Data Sheet - Page 203
CacheRelated Signals, 7.4 Cache Disabling and Flushing
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 35 describes how the CACHE# signal is driven based on the cycle type, the CI bit of TR12, the PCD signal, and the UWCCR model-specific register. Table 35. CACHE# Signal Generation Cycle Type CI Bit of TR12 PCD Signal Access Within WC/UC Range* CACHE# Writebacks X X X Low Unlocked Reads 0 0 0 Low Locked Reads X X X High Single Writes X X X High Any Cycle Except Writebacks 1 X X High Any Cycle Except Writebacks X 1 X High Any Cycle Except Writebacks X X 1 High Note: * WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR, and only applies to the AMD-K6-2 processor Model 8/[F:8]. Cache-Related Signals Complete descriptions of the signals that control cacheability and cache coherency are given on the following pages: s CACHE#-page 96 s EADS#-page 100 s FLUSH#-page 103 s HIT#-page 104 s HITM#-page 104 s INV-page 108 s KEN#-page 109 s PCD-page 113 s PWT-page 115 s WB/WT#-page 123 7.4 Cache Disabling and Flushing To completely disable all cache accesses, the CD bit must be set to 1 and the cache must be completely flushed. There are three different methods for flushing the cache. The first method relies on the system logic and other two methods rely on software. Chapter 7 Cache Organization 183