AMD AMD-K6-2/500AFX Data Sheet - Page 180

Locked Operation with BOFF# Intervention, In the processor immediately restarts the aborted

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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Locked Operation with BOFF# Intervention Figure 70 shows BOFF# asserted within a locked read-write pair of bus cycles. In this example, the processor asserts LOCK# with ADS# to drive a locked memory read cycle followed by a locked memory write cycle. During the locked memory write cycle in this example, the processor samples BOFF# asserted. The processor immediately aborts the locked memory write cycle and floats all its bus-driving signals, including LOCK#. The system logic or another bus master can initiate an inquire cycle or drive a new bus cycle one clock edge after the clock edge on which BOFF# is sampled asserted. If the system logic drives a BOFF#-initiated inquire cycle and hits a modified line, the processor performs a writeback cycle before it restarts the locked cycle (the processor asserts LOCK# during the writeback cycle). In Figure 70, the processor immediately restarts the aborted locked write cycle by driving the bus off the clock edge on which BOFF# is sampled negated. The system logic must ensure the processor results for interrupted and uninterrupted locked cycles are consistent. That is, the system logic must guarantee the memory accessed by the processor is not modified during the time another bus master controls the bus. 160 Bus Cycles Chapter 5

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160
Bus Cycles
Chapter 5
AMD-K6
®
-2 Processor Data Sheet
21850J/0—February 2000
Preliminary Information
Locked Operation
with BOFF#
Intervention
Figure 70 shows BOFF# asserted within a locked read-write pair
of bus cycles. In this example, the processor asserts LOCK#
with ADS# to drive a locked memory read cycle followed by a
locked memory write cycle. During the locked memory write
cycle in this example, the processor samples BOFF# asserted.
The processor immediately aborts the locked memory write
cycle and floats all its bus-driving signals, including LOCK#.
The system logic or another bus master can initiate an inquire
cycle or drive a new bus cycle one clock edge after the clock
edge on which BOFF# is sampled asserted. If the system logic
drives a BOFF#-initiated inquire cycle and hits a modified line,
the processor performs a writeback cycle before it restarts the
locked cycle (the processor asserts LOCK# during the
writeback cycle).
In Figure 70, the processor immediately restarts the aborted
locked write cycle by driving the bus off the clock edge on
which BOFF# is sampled negated. The system logic must ensure
the processor results for interrupted and uninterrupted locked
cycles are consistent. That is, the system logic must guarantee
the memory accessed by the processor is not modified during
the time another bus master controls the bus.