AMD AMD-K6-2/500AFX Data Sheet - Page 215

21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet FLUSH# PFIR If an internal snoop hits its target, the processor does the following: s Data cache snoop during an instruction-cache read miss-If modified, the line in the data cache is written back on the system bus to external memory. Regardless of its state, the data-cache line is invalidated and the instruction cache performs a burst read cycle from external memory. s Instruction cache snoop during a data cache miss-The line in the instruction cache is marked invalid, and the data-cache read or write is performed as defined in Table 36 on page 193. In response to sampling FLUSH# asserted, the processor writes back any data cache lines that are in the modified state and then marks all lines in the instruction and data caches as invalid. The AMD-K6-2 processor Model 8/[F:8] processor contains the Page Flush/Invalidate Register (PFIR) that allows cache invalidation and optional flushing of a specific 4-Kbyte page from the linear address space (see Figure 82). When the PFIR is written to (using the WRMSR instruction), the invalidation and, optionally, the flushing begins. The total amount of cache in the AMD-K6-2 processor is 64 Kbytes. Using this register can result in a much lower cycle count for flushing particular pages versus flushing the entire cache. 63 32 31 12 11 9 8 7 10 LINPAGE P F F / I Symbol LINPAGE PF F/I Reserved Description 20-bit Linear Page Address Page Fault Occurred Flush/Invalidate Command Bit 31-12 8 0 Figure 82. Page Flush/Invalidate Register (PFIR)-MSR C000_0088h LINPAGE. This 20-bit field must be written with bits 31:12 of the linear address of the 4-Kbyte page that is to be invalidated and optionally flushed from the L1 cache. Chapter 7 Cache Organization 195