AMD AMD-K6-2/500AFX Data Sheet - Page 141
TRST# (Test Reset), 4.51 VCC2DET (VCC2 Detect), 4.52 VCC2H/L# (VCC2 High/Low
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.50 Summary Sampled TRST# (Test Reset) Input, Internal Pullup The assertion of TRST# initializes the Test Access Port (TAP) by resetting its state machine to the Test-Logic-Reset state. See "Boundary-Scan Test Access Port (TAP)" on page 223 for details regarding the operation of the TAP controller. TRST# is a completely asynchronous input that does not require a minimum setup and hold time relative to TCK. See Table 69 on page 280 for the minimum pulse width requirement. 4.51 Summary Driven VCC2DET (VCC2 Detect) Output VCC2DET is internally tied to VSS (logic level 0) to indicate to the system logic that it must supply the specified dual-voltage requirements to the VCC2 and VCC3 pins. The VCC2 pins supply voltage to the processor core, independent of the voltage supplied to the I/O buffers on the VCC3 pins. Upon sampling VCC2DET Low, system logic should sample VCC2H/L# to identify core voltage requirements. VCC2DET always equals 0 and is never floated-even during the Tri-State Test mode. 4.52 Summary Driven VCC2H/L# (VCC2 High/Low) Output VCC2H/L# is internally tied to VSS (logic level 0) to indicate to the system logic that it must supply the specified processor core voltage to the VCC2 pins. The VCC2 pins supply voltage to the processor core, independent of the voltage supplied to the I/O buffers on the VCC3 pins. Upon sampling VCC2DET Low to identify dual-voltage processor requirements, system logic should sample VCC2H/L# to identify the core voltage requirements for 2.9 V and 3.2 V products (High) or 2.2 V and 2.4 V products (Low). VCC2H/L# always equals 0 and is never floated for 2.2 V and 2.4 V products-even during the Tri-State Test mode. To ensure proper operation for 2.9V and 3.2V products, system logic that Chapter 4 Signal Descriptions 121