AMD AMD-K6-2/500AFX Data Sheet - Page 261
Debug Exceptions, Table 51., DR7 LEN and RW Definitions
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Debug Exceptions The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the operation of the processor and are provided in order to be software compatible with previous generations of x86 processors. When set to 1, the GD bit in DR7 (bit 13) enables the debug exception associated with the BD bit (bit 13) in DR6. This bit is set to 0 when a debug exception is generated. LEN3-LEN0 and RW3-RW0 are two-bit fields in DR7 that specify the length and type of each breakpoint as defined in Table 51. Table 51. DR7 LEN and RW Definitions LEN Bits1 RW Bits Breakpoint 00b 00b2 Instruction Execution 00b One-byte Data Write 01b 01b Two-byte Data Write 11b Four-byte Data Write 00b One-byte I/O Read or Write 01b 10b3 Two-byte I/O Read or Write 11b Four-byte I/O Read or Write 00b One-byte Data Read or Write 01b 11b Two-byte Data Read or Write 11b Four-byte Data Read or Write Notes: 1. LEN bits equal to 10b is undefined. 2. When RW equals 00b, LEN must be equal to 00b. 3. When RW equals 10b, debugging extensions (DE) must be enabled (bit 3 of CR4 must be set to 1). If DE is set to 0, then RW equal to 10b is undefined. A debug exception is categorized as either a debug trap or a debug fault. A debug trap calls the debugger following the execution of the instruction that caused the trap. A debug fault calls the debugger prior to the execution of the instruction that caused the fault. All debug traps and faults generate either an Interrupt 01h or an Interrupt 03h exception. Chapter 11 Test and Debug 241