AMD AMD-K6-2/500AFX Data Sheet - Page 298
RESET and Test Signal Timing
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 16.9 RESET and Test Signal Timing Table 67. RESET and Configuration Signals for 100-MHz Bus Operation Symbol Parameter Description Preliminary Data Figure Min Max Comments t90 RESET Setup Time 1.7 ns 100 t91 RESET Hold Time 1.0 ns 100 t92 RESET Pulse Width, VCC and CLK Stable 15 clocks 100 t93 RESET Active After VCC and CLK Stable 1.0 ms 100 t94 BF[2:0] Setup Time 1.0 ms 100 Note 3 t95 BF[2:0] Hold Time 2 clocks 100 Note 3 t96 BRDYC# Hold Time 1.0 ns 100 Note 4 t97 BRDYC# Setup Time 2 clocks 100 Note 2 t98 BRDYC# Hold Time 2 clocks 100 Note 2 t99 FLUSH# Setup Time 1.7 ns 100 Note 1 t100 FLUSH# Hold Time 1.0 ns 100 Note 1 t101 FLUSH# Setup Time 2 clocks 100 Note 2 t102 FLUSH# Hold Time 2 clocks 100 Note 2 Notes: 1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is sampled negated. 2. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of RESET. 3. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET. 4. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET. 278 Signal Switching Characteristics Chapter 16