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Table 48., Boundary Scan Bit Definitions for Model 8/[F:8 - 200

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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 48. Boundary Scan Bit Definitions for Model 8/[F:8] Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable 280 D35_E 247 D19 214 BF1 181 A24 148 A14 115 BE7# 279 D35 246 D16_E 213 BF2 180 A18_E 147 A17_E 114 PCD_E 278 D29_E 245 D16 212 RESET 179 A18 146 A17 113 PCD 277 D29 244 D17_E 211 BF0 178 A5_E 145 A16_E 112 DC_E 276 D33_E 243 D17 210 FLUSH# 177 A5 144 A16 111 D/C# 275 D33 242 D15_E 209 INTR 176 EADS# 143 HIT_E 110 WR_E 274 D27_E 241 D15 208 NMI 175 A22_E 142 HIT# 109 W/R# 273 D27 240 DP1_E 207 SMI# 174 A22 141 ADS_E 108 NA# 272 DP0_E 239 DP1 206 A25_E 173 AHOLD 140 ADS# 107 PWT_E 271 DP0 238 D13_E 205 A25 172 HITM_E 139 CLK 106 PWT 270 DP3_E 237 D13 204 A26_E 171 HITM# 138 ADSC_E 105 CACHE_E 269 DP3 236 D6_E 203 A26 170 A4_E 137 ADSC# 104 CACHE# 268 D25_E 235 D6 202 A29_E 169 A4 136 BE0_E 103 WB/WT# 267 D25 234 D14_E 201 A29 168 A9_E 135 BE0# 102 MIO_E 266 D0_E 233 D14 200 A28_E 167 A9 134 AP_E 101 M/IO# 265 D0 232 D11_E 199 A28 166 A8_E 133 AP 100 BREQ_E 264 D30_E 231 D11 198 A23_E 165 A8 132 BE1_E 99 BREQ 263 D30 230 D1_E 197 A23 164 A19_E 131 BE1# 98 SCYC_E 262 DP2_E 229 D1 196 A27_E 163 A19 130 BE2_E 97 SCYC 261 DP2 228 D12_E 195 A27 162 BOFF# 129 BE2# 96 LOCK_E 260 D2_E 227 D12 194 A11_E 161 A6_E 128 BRDY# 95 LOCK# 259 D2 226 D10_E 193 A11 160 A6 127 BE3_E 94 APCHK_E 258 D28_E 225 D10 192 A3_E 159 A20_E 126 BE3# 93 APCHK# 257 D28 224 D7_E 191 A3 158 A20 125 BE4_E 92 PCHK_E 256 D24_E 223 D7 190 A31_E 157 A13_E 124 BE4# 91 PCHK# 255 D24 222 D8_E 189 A31 156 A13 123 BRDYC# 90 EWBE# 254 D26_E 221 D8 188 A21_E 155 A12_E 122 BE5_E 89 SMIACT_E 253 D26 220 D9_E 187 A21 154 A12 121 BE5# 88 SMIACT# 252 D21_E 219 D9 186 A30_E 153 A10_E 120 BE6_E 87 FERR_E 251 D21 218 HOLD 185 A30 152 A10 119 BE6# 86 FERR# 250 D18_E 217 STPCLK# 184 A7_E 151 A15_E 118 KEN# 85 D20_E 249 D18 216 INIT 183 A7 150 A15 117 INV 84 D20 248 D19_E 215 IGNNE# 182 A24_E 149 A14_E 116 BE7_E 83 D22_E Chapter 11 Test and Debug 229

Section	Page
Contents	3
List of Figures	11
List of Tables	15
Revision History	19
1 AMDK6®2 Processor	21
1.1 Super7™ Platform Initiative	23
Super7™ Platform Enhancements	23
Super7™ Platform Advantages	24
2 Internal Architecture	25
2.1 Introduction	25
2.2 AMDK6®2 Processor Microarchitecture Overview	25
Enhanced RISC86® Microarchitecture	26
2.3 Cache, Instruction Prefetch, and Predecode Bits	29
Cache	29
Prefetching	30
Predecode Bits	30
2.4 Instruction Fetch and Decode	31
Instruction Fetch	31
Instruction Decode	32
2.5 Centralized Scheduler	34
2.6 Execution Units	35
Register X and Y Pipelines	36
2.7 BranchPrediction Logic	37
Branch History Table	38
Branch Target Cache	38
Return Address Stack	38
Branch Execution Unit	39
3 Software Environment	41
3.1 Registers	41
GeneralPurpose Registers	42
Integer Data Types	43
Segment Registers	44
Segment Usage	44
Instruction Pointer	45
FloatingPoint Registers	45
FloatingPoint Register Data Types	48
MMX™/3DNow!™ Registers	49
MMX™ Data Types	49
3DNow!™ Data Types	50
EFLAGS Register	51
Control Registers	52
Debug Registers	54
ModelSpecific Registers (MSR)	57
Memory Management Registers	60
Task State Segment	62
Paging	63
Descriptors and Gates	66
Exceptions and Interrupts	69
3.2 AMDK6®2 Processor Model 8/[F:8] Registers	70
Extended Feature Enable Register (EFER)–Model 8/[F:8]	70
Write Handling Control Register (WHCR)–Model 8/[F:8]	71
UC/WC Cacheability Control Register (UWCCR)	72
Processor State Observability Register (PSOR)	73
Page Flush/Invalidate Register (PFIR)	73
3.3 Instructions Supported by the AMDK6®2 Processor	74
4 Signal Descriptions	103
4.1 Signal Terminology	103
4.2 A20M# (Address Bit 20 Mask)	105
4.3 A[31:3] (Address Bus)	106
4.4 ADS# (Address Strobe)	107
4.5 ADSC# (Address Strobe Copy)	107
4.6 AHOLD (Address Hold)	108
4.7 AP (Address Parity)	109
4.8 APCHK# (Address Parity Check)	110
4.9 BE[7:0]# (Byte Enables)	111
4.10 BF[2:0] (Bus Frequency)	112
4.11 BOFF# (Backoff)	113
4.12 BRDY# (Burst Ready)	114
4.13 BRDYC# (Burst Ready Copy)	115
4.14 BREQ (Bus Request)	116
4.15 CACHE# (Cacheable Access)	116
4.16 CLK (Clock)	117
4.17 D/C# (Data/Code)	117
4.18 D[63:0] (Data Bus)	118
4.19 DP[7:0] (Data Parity)	119
4.20 EADS# (External Address Strobe)	120
4.21 EWBE# (External Write Buffer Empty)	121
4.22 FERR# (FloatingPoint Error)	122
4.23 FLUSH# (Cache Flush)	123
4.24 HIT# (Inquire Cycle Hit)	124
4.25 HITM# (Inquire Cycle Hit To Modified Line)	124
4.26 HLDA (Hold Acknowledge)	125
4.27 HOLD (Bus Hold Request)	125
4.28 IGNNE# (Ignore Numeric Exception)	126
4.29 INIT (Initialization)	127
4.30 INTR (Maskable Interrupt)	128
4.31 INV (Invalidation Request)	128
4.32 KEN# (Cache Enable)	129
4.33 LOCK# (Bus Lock)	130
4.34 M/IO# (Memory or I/O)	131
4.35 NA# (Next Address)	132
4.36 NMI (NonMaskable Interrupt)	132
4.37 PCD (Page Cache Disable)	133
4.38 PCHK# (Parity Check)	134
4.39 PWT (Page Writethrough)	135
4.40 RESET (Reset)	136
4.41 RSVD (Reserved)	136
4.42 SCYC (Split Cycle)	137
4.43 SMI# (System Management Interrupt)	137
4.44 SMIACT# (System Management Interrupt Active)	138
4.45 STPCLK# (Stop Clock)	139
4.46 TCK (Test Clock)	139
4.47 TDI (Test Data Input)	140
4.48 TDO (Test Data Output)	140
4.49 TMS (Test Mode Select)	140
4.50 TRST# (Test Reset)	141
4.51 VCC2DET (VCC2 Detect)	141
4.52 VCC2H/L# (VCC2 High/Low)	141
4.53 W/R# (Write/Read)	142
4.54 WB/WT# (Writeback or Writethrough)	143
5 Bus Cycles	147
5.1 Timing Diagrams	147
5.2 Bus State Machine Diagram	149
Idle	150
Address	150
Data	150
DataNA# Requested	150
Pipeline Address	150
Pipeline Data	151
Transition	151
5.3 Memory Reads and Writes	152
SingleTransfer Memory Read and Write	152
Misaligned SingleTransfer Memory Read and Write	154
Burst Reads and Pipelined Burst Reads	156
Burst Writeback	158
5.4 I/O Read and Write	160
Basic I/O Read and Write	160
Misaligned I/O Read and Write	161
5.5 Inquire and Bus Arbitration Cycles	162
Hold and Hold Acknowledge Cycle	162
HOLDInitiated Inquire Hit to Shared or Exclusive Line	164
HOLDInitiated Inquire Hit to Modified Line	166
AHOLDInitiated Inquire Miss	168
AHOLDInitiated Inquire Hit to Shared or Exclusive Line	170
AHOLDInitiated Inquire Hit to Modified Line	172
AHOLD Restriction	174
Bus Backoff (BOFF#)	176
Locked Cycles	178
Basic Locked Operation	178
Locked Operation with BOFF# Intervention	180
Interrupt Acknowledge	182
5.6 Special Bus Cycles	184
Basic Special Bus Cycle	184
Shutdown Cycle	186
Stop Grant and Stop Clock States	187
INITInitiated Transition from Protected Mode to Real Mode	190
6 Poweron Configuration and Initialization	193
6.1 Signals Sampled During the Falling Transition of RESET	193
FLUSH#	193
BF[2:0]	193
BRDYC#	193
6.2 RESET Requirements	194
6.3 State of Processor After RESET	194
Output Signals	194
Registers	194
6.4 State of Processor After INIT	197
7 Cache Organization	199
7.1 MESI States in the Data Cache	200
7.2 Predecode Bits	200
7.3 Cache Operation	201
CacheRelated Signals	203
7.4 Cache Disabling and Flushing	203
7.5 CacheLine Fills	204
7.6 CacheLine Replacements	205
7.7 Write Allocate	206
Write to a Cacheable Page	206
Write to a Sector	207
Write Allocate Limit	207
Write Allocate Logic Mechanisms and Conditions	209
7.8 Prefetching	212
Hardware Prefetching	212
Software Prefetching	212
7.9 Cache States	212
7.10 Cache Coherency	214
Inquire Cycles	214
Internal Snooping	214
FLUSH#	215
PFIR	215
WBINVD and INVD	216
CacheLine Replacement	216
Cache Snooping	218
7.11 Writethrough versus Writeback Coherency States	219
7.12 A20M# Masking of Cache Accesses	219
8 Write Merge Buffer	221
8.1 EWBE Control	221
8.2 Memory Type Range Registers	223
UC/WC Cacheability Control Register (UWCCR)	223
9 FloatingPoint and Multimedia Execution Units	227
9.1 FloatingPoint Execution Unit	227
Handling FloatingPoint Exceptions	227
External Logic Support of FloatingPoint Exceptions	227
9.2 Multimedia and 3DNow!™ Execution Units	229
9.3 FloatingPoint and MMX™/3DNow!™ Instruction Compatibility	229
Registers	229
Exceptions	229
FERR# and IGNNE#	229
10 System Management Mode (SMM)	231
10.1 Overview	231
10.2 SMM Operating Mode and Default Register Values	231
10.3 SMM StateSave Area	234
10.4 SMM Revision Identifier	236
10.5 SMM Base Address	237
10.6 Halt Restart Slot	237
10.7 I/O Trap Dword	238
10.8 I/O Trap Restart Slot	239
10.9 Exceptions, Interrupts, and Debug in SMM	240
11 Test and Debug	241
11.1 BuiltIn SelfTest (BIST)	241
11.2 TriState Test Mode	242
11.3 BoundaryScan Test Access Port (TAP)	243
Test Access Port	243
TAP Signals	243
TAP Registers	244
TAP Instructions	251
TAP Controller State Machine	252
11.4 L1 Cache Inhibit	255
Purpose	255
11.5 Debug	256
Debug Registers	256
Debug Exceptions	261
12 Clock Control	263
12.1 Halt State	264
Enter Halt State	264
Exit Halt State	264
12.2 Stop Grant State	265
Enter Stop Grant State	265
Exit Stop Grant State	265
12.3 Stop Grant Inquire State	266
Enter Stop Grant Inquire State	266
Exit Stop Grant Inquire State	266
12.4 Stop Clock State	266
Enter Stop Clock State	266
Exit Stop Clock State	267
13 Power and Grounding	269
13.1 Power Connections	269
13.2 Decoupling Recommendations	270
13.3 Pin Connection Requirements	271
14 Electrical Data	273
14.1 Electrical Data for OPN Suffixes AHX, 400AFQ, and AFR	273
Operating Ranges	273
Absolute Ratings	274
DC Characteristics	274
Power Dissipation	277
14.2 Electrical Data for OPN Suffixes AGR, AFX, and 400AFR	278
Operating Ranges	278
Absolute Ratings	279
DC Characteristics	279
Power Dissipation	282
15 I/O Buffer Characteristics	283
15.1 Selectable Drive Strength	283
15.2 I/O Buffer Model	284
15.3 I/O Model Application Note	285
15.4 I/O Buffer AC and DC Characteristics	285
16 Signal Switching Characteristics	287
16.1 CLK Switching Characteristics	287
16.2 Clock Switching Characteristics for 100MHz Bus Operation	288
16.3 Clock Switching Characteristics for 66MHz Bus Operation	288
16.4 Valid Delay, Float, Setup, and Hold Timings	289
16.5 Output Delay Timings for 100MHz Bus Operation	290
16.6 Input Setup and Hold Timings for 100MHz Bus Operation	292
16.7 Output Delay Timings for 66MHz Bus Operation	294
16.8 Input Setup and Hold Timings for 66MHz Bus Operation	296
16.9 RESET and Test Signal Timing	298
17 Thermal Design	305
17.1 Package Thermal Specifications	305
Heat Dissipation Path	310
Measuring Case Temperature	310
17.2 Layout and Airflow Considerations	311
Voltage Regulator	311
Airflow Management in a System Design	312
18 Pin Description Diagram	315
19 Pin Designations	317
20 Package Specifications	319
20.1 321Pin Staggered CPGA Package Specification	319
21 Ordering Information	321

Match case Limit results 1 per page

Chapter 11

Test and Debug

229

21850J/0—February 2000

AMD-K6

-2 Processor Data Sheet

Preliminary Information

Table 48.

Boundary Scan Bit Definitions for Model 8/[F:8]

Bit

Pin/Enable

Bit

Pin/Enable

Bit

Pin/Enable

Bit

Pin/Enable

Bit

Pin/Enable

Bit

Pin/Enable

280

D35_E

247

D19

214

BF1

181

A24

148

A14

115

BE7#

279

D35

246

D16_E

213

BF2

180

A18_E

147

A17_E

114

PCD_E

278

D29_E

245

D16

212

RESET

179

A18

146

A17

113

PCD

277

D29

244

D17_E

211

BF0

178

A5_E

145

A16_E

112

DC_E

276

D33_E

243

D17

210

FLUSH#

177

144

A16

111

D/C#

275

D33

242

D15_E

209

INTR

176

EADS#

143

HIT_E

110

WR_E

274

D27_E

241

D15

208

NMI

175

A22_E

142

HIT#

109

W/R#

273

D27

240

DP1_E

207

SMI#

174

A22

141

ADS_E

108

NA#

272

DP0_E

239

DP1

206

A25_E

173

AHOLD

140

ADS#

107

PWT_E

271

DP0

238

D13_E

205

A25

172

HITM_E

139

CLK

106

PWT

270

DP3_E

237

D13

204

A26_E

171

HITM#

138

ADSC_E

105

CACHE_E

269

DP3

236

D6_E

203

A26

170

A4_E

137

ADSC#

104

CACHE#

268

D25_E

235

202

A29_E

169

136

BE0_E

103

WB/WT#

267

D25

234

D14_E

201

A29

168

A9_E

135

BE0#

102

MIO_E

266

D0_E

233

D14

200

A28_E

167

134

AP_E

101

M/IO#

265

232

D11_E

199

A28

166

A8_E

133

100

BREQ_E

264

D30_E

231

D11

198

A23_E

165

132

BE1_E

BREQ

263

D30

230

D1_E

197

A23

164

A19_E

131

BE1#

SCYC_E

262

DP2_E

229

196

A27_E

163

A19

130

BE2_E

SCYC

261

DP2

228

D12_E

195

A27

162

BOFF#

129

BE2#

LOCK_E

260

D2_E

227

D12

194

A11_E

161

A6_E

128

BRDY#

LOCK#

259

226

D10_E

193

A11

160

127

BE3_E

APCHK_E

258

D28_E

225

D10

192

A3_E

159

A20_E

126

BE3#

APCHK#

257

D28

224

D7_E

191

158

A20

125

BE4_E

PCHK_E

256

D24_E

223

190

A31_E

157

A13_E

124

BE4#

PCHK#

255

D24

222

D8_E

189

A31

156

A13

123

BRDYC#

EWBE#

254

D26_E

221

188

A21_E

155

A12_E

122

BE5_E

SMIACT_E

253

D26

220

D9_E

187

A21

154

A12

121

BE5#

SMIACT#

252

D21_E

219

186

A30_E

153

A10_E

120

BE6_E

FERR_E

251

D21

218

HOLD

185

A30

152

A10

119

BE6#

FERR#

250

D18_E

217

STPCLK#

184

A7_E

151

A15_E

118

KEN#

D20_E

249

D18

216

INIT

183

150

A15

117

INV

D20

248

D19_E

215

IGNNE#

182

A24_E

149

A14_E

116

BE7_E

D22_E