AMD AMD-K6-2/500AFX Data Sheet - Page 137
SCYC (Split Cycle), 4.43 SMI# (System Management Interrupt), Output, Input, Internal Pullup
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.42 SCYC (Split Cycle) Output Summary The processor asserts SCYC during misaligned, locked transfers on the D[63:0] data bus. The processor generates additional bus cycles to complete the transfer of misaligned data. Driven and Floated For purposes of bus cycles, the term aligned means: s Any 1-byte transfers s 2-byte and 4-byte transfers that lie within 4-byte address boundaries s 8-byte transfers that lie within 8-byte address boundaries SCYC is asserted off the same clock edge as ADS#, and negated off the clock edge on which NA# or the last expected BRDY# of the entire locked sequence is sampled asserted. SCYC is only valid during locked memory cycles. SCYC is floated off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD. 4.43 Summary SMI# (System Management Interrupt) Input, Internal Pullup The assertion of SMI# causes the processor to enter System Management Mode (SMM). Upon recognizing SMI#, the processor performs the following actions, in the order shown: 1. Flushes its instruction pipelines 2. Completes all pending and in-progress bus cycles 3. Acknowledges the interrupt by asserting SMIACT# after sampling EWBE# asserted (if EWBE# is masked off, then SMIACT# is not affected by EWBE#) 4. Saves the internal processor state in SMM memory 5. Disables interrupts by clearing the interrupt flag (IF) in EFLAGS and disables NMI interrupts 6. Jumps to the entry point of the SMM service routine at the SMM base physical address which defaults to 0003_8000h in SMM memory Chapter 4 Signal Descriptions 117