AMD AMD-K6-2/500AFX Data Sheet - Page 35
Execution Units, units-store, load, integer X ALU, MMX ALU - multiplier
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet RISC86 #0 From Decode Logic RISC86 #1 RISC86 #2 RISC86 #3 Centralized RISC86® Operation Scheduler RISC86 Issue Buses RISC86 Operation Buffer Figure 5. AMD-K6®-2 Processor Scheduler 2.6 Execution Units The AMD-K6-2 processor contains ten parallel execution units-store, load, integer X ALU, integer Y ALU, MMX ALU (X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU, floating-point, and branch condition. Each unit is independent and capable of handling the RISC86 operations. Table 1 on page 16 details the execution units, functions performed within these units, operation latency, and operation throughput. The store and load execution units are two-stage pipelined designs. The store unit performs data writes and register calculation for LEA/PUSH. Data memory and register writes from stores are available after one clock. Store operations are held in a store queue prior to execution. From there, they execute in order. The load unit performs data memory reads. Data is available from the load unit after two clocks. Chapter 2 Internal Architecture 15