AMD AMD-K6-2/500AFX Data Sheet - Page 205
CacheLine Replacements, Cache Organization, AMD-K6, 2 Processor Data Sheet
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 7.6 Chapter 7 The processor does not cache certain memory accesses such as locked operations. In addition, the processor does not cache PDE or PTE memory reads in the L1 cache (referred to as page table walks). When the processor needs to read memory, the processor drives a read cycle onto the bus. If the cycle is cacheable, the processor asserts CACHE#. If the cycle is not cacheable, a non-burst, single-transfer read takes place. The processor waits for the system logic to return the data and assert a single BRDY# (See Figure 55 on page 133). If the cycle is cacheable, the processor executes a 32-byte burst read cycle. The processor expects a total of four BRDY# signals for a burst read cycle to take place (See Figure 57 on page 137). Cache-line fills initiate 32-byte burst read cycles from memory on the system bus for the instruction cache and the data cache. If a data-cache line being filled replaces a modified line, the modified contents of the line are copied to a 32-byte writeback (copyback) buffer in the bus interface unit while the new line is being read. Cache-Line Replacements As programs execute and task switches occur, some cache lines eventually require replacement. Instruction cache lines are replaced using a Least Recently Used (LRU) algorithm. If line replacement is required, lines are replaced when read cache misses occur. The data cache uses a slightly different approach to line replacement. If a miss occurs, and a replacement is required, lines are replaced by using a Least Recently Allocated (LRA) algorithm. Two forms of cache misses and associated cache fills can take place-a tag-miss cache fill and a tag-hit cache fill. In the case of a tag-miss cache fill, the miss is due to a tag mismatch, in which case the required cache line is filled from external memory, and the cache line within the sector that was not required is marked as invalid. In the case of a tag-hit cache fill, the address matches the tag, but the requested cache line is marked as invalid. The required cache line is filled from external memory, and the cache line within the sector that is not required remains in the same cache state. Cache Organization 185