AMD AMD-K6-2/500AFX Data Sheet - Page 21
AMDK6®2 Processor - 3d
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 1 AMD-K6®-2 Processor s Advanced 6-Issue RISC86® Superscalar Microarchitecture x Ten parallel specialized execution units x Multiple sophisticated x86-to-RISC86 instruction decoders x Advanced two-level branch prediction x Speculative execution x Out-of-order execution x Register renaming and data forwarding x Issues up to six RISC86 instructions per clock s Large Internal Split 64-Kbyte Level-One (L1) Cache x 32-Kbyte instruction cache with additional 20-Kbytes of predecode cache x 32-Kbyte writeback dual-ported data cache x Two-way set associative x MESI protocol support s 3DNow!™ Technology x Additional instructions to improve 3D graphics and multimedia performance x Separate multiplier and ALU for superscalar instruction execution s Compatible with Super7™ platform x Leverages high-speed 100-MHz processor bus x Accelerated Graphic Port (AGP) support s High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit s High-Performance Industry-Standard MMX™ Instructions x Dual integer ALU for superscalar execution s 321-Pin Ceramic Pin Grid Array (CPGA) Package s Industry-Standard System Management Mode (SMM) s IEEE 1149.1 Boundary Scan s x86 Binary Software Compatibility The innovative AMD-K6®-2 processor brings industry-leading performance to PC systems running the extensive installed base of x86 software. Its Super7™ compatible, 321-pin ceramic pin grid array (CPGA) package enables the processor to reduce time-to-market by leveraging today's cost-effective industry-standard infrastructure to deliver a superior-performing PC solution. Chapter 1 AMD-K6®-2 Processor 1