AMD AMD-K6-2/500AFX Data Sheet - Page 37
BranchPrediction Logic, Scheduler, Buffer, Issue Bus, for the, Register X, Execution, Pipeline
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Scheduler Buffer (24 RISC86® Operations) Issue Bus for the Register X Execution Pipeline Issue Bus for the Register Y Execution Pipeline Integer X ALU MMX™ ALU MMX/ 3DNow!™ Multiplier MMX Shifter 3DNow! ALU MMX ALU Integer Y ALU Figure 6. Register X and Y Functional Units The branch condition unit is separate from the branch prediction logic in that it resolves conditional branches such as JCC and LOOP after the branch condition has been evaluated. 2.7 Branch-Prediction Logic Sophisticated branch logic that can minimize or hide the impact of changes in program flow is designed into the AMD-K6-2 processor. Branches in x86 code fit into two categories - unconditional branches, which always change program flow (that is, the branches are always taken) and conditional branches, which may or may not divert program flow (that is, the branches are taken or not-taken). When a conditional branch is not taken, the processor simply continues decoding and executing the next instructions in memory. Typical applications have up to 10% of unconditional branches and another 10% to 20% conditional branches. The AMD-K6-2 processor branch logic has been designed to handle this type of Chapter 2 Internal Architecture 17