Intel BFCBASE Data Sheet

Intel BFCBASE - Motherboard - 7300 Manual

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  • Intel BFCBASE | Data Sheet - Page 1
    Series and 7300 Series Datasheet September 2008 Notice: The Intel® Xeon® Processor 7200 Series and 7300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Document
  • Intel BFCBASE | Data Sheet - Page 2
    ://www.intel.com. Intel, Pentium, Intel Xeon, Intel SpeedStep, Intel Core, and Intel Virtualization Technology, are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Intel® 64 requires a computer system with a processor, chipset
  • Intel BFCBASE | Data Sheet - Page 3
    Absolute Maximum and Minimum Ratings 23 2.11 Processor DC Specifications 24 2.11.1 Flexible Motherboard Guidelines (FMB 25 2.11.2 Platform Environmental Control Interface (PECI) DC Specifications 35 2.11.3 VCC Overshoot Specification 37 2.11.4 AGTL+ FSB Specifications 38 2.12 Front Side Bus AC
  • Intel BFCBASE | Data Sheet - Page 4
    PIROM and Scratch EEPROM Supported SMBus Transactions 118 7.4.3 Processor Information ROM (PIROM 119 7.4.4 Checksums 137 7.4.5 Scratch EEPROM 137 8 Boxed Processor Specifications 139 8.1 Introduction ...139 8.2 Thermal Specifications 139 8.2.1 Boxed Processor Cooling Requirements 139 9 Debug
  • Intel BFCBASE | Data Sheet - Page 5
    Clock Crosspoint Specification 47 2-15 BCLK Waveform at Processor Pad and Pin Core Intel® Xeon® E7300 Processor Thermal Profile 97 6-2 Quad-Core Intel® Xeon® X7350 Processor Thermal Profile 98 6-3 Quad-Core Intel® Xeon® L7345 Processor Thermal Profile 100 6-4 Dual-Core Intel® Xeon® Processor
  • Intel BFCBASE | Data Sheet - Page 6
    Core Intel® Xeon® X7350 Processor Thermal Specifications 98 6-4 Quad-Core Intel® Xeon® X7350 Processor Thermal Profile Table 99 6-5 Quad-Core Intel® Xeon® L7345 Processor Thermal Specifications 99 6-6 Quad-Core Intel® Xeon® L7345 Processor Thermal Profile 100 6-7 Dual-Core Intel® Xeon® Processor
  • Intel BFCBASE | Data Sheet - Page 7
    7-2 Extended HALT Maximum Power 113 7-3 Memory Device SMBus Addressing 118 7-4 Read Byte SMBus Packet 118 7-5 Write Byte SMBus Packet 118 7-6 Processor Information ROM Data Sections 119 7-7 128 Byte ROM Checksum Values 137 Document Number: 318080-002 7
  • Intel BFCBASE | Data Sheet - Page 8
    • Changed Product Name to Intel® Xeon® Processor 7200 Series and 7300 Series • Updated Power Specifications • The character byte ordering the integrated heat spreader (IHS). This feature, which supports anti-mixing, may be seen on some processor packages. There are no major electrical, mechanical,
  • Intel BFCBASE | Data Sheet - Page 9
    a separate register for data movement. SSE3 instructions provide highly efficient doubleprecision floating point, SIMD integer, and memory management operations. The Intel® Xeon® Processor 7200 Series and 7300 Series support Intel® 64 as an enhancement to Intel's IA-32 architecture. This enhancement
  • Intel BFCBASE | Data Sheet - Page 10
    Zero Insertion Force (ZIF) mPGA604 socket. The Intel® Xeon® Processor 7200 Series and 7300 Series support 40-bit addressing. Table 1-1. Quad-Core Intel® Xeon® Processor 7300 Series Processor Features # of Processor Cores 4 L1 Cache per core 32 KB instruction 32 KB data L2 Advanced Transfer Cache
  • Intel BFCBASE | Data Sheet - Page 11
    FSB speeds and bandwidth. • Flexible Motherboard Guidelines (FMB) - Are estimates of the maximum values the Intel® Xeon® Processor 7200, 7300 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. • Functional Operation
  • Intel BFCBASE | Data Sheet - Page 12
    IA-32. This 64-bit instruction set architecture was formerly known as IA-32 with EM64T or Intel® EM64T. • Platform Environment Control Interface (PECI) - A proprietary one-wire bus interface that provides a communication channel between Intel processor and chipset components to external thermal
  • Intel BFCBASE | Data Sheet - Page 13
    AP-485, Intel® Processor Identification and the CPUID Instruction Intel® 64 and IA-32 Architectures Software Developer's Manual • Volume 1: Basic Architecture • Volume 2A: Instruction Set Reference, A-M • Volume 2B: Instruction Set Reference, N-Z • Volume 3A: System Programming Guide Part 1 • Volume
  • Intel BFCBASE | Data Sheet - Page 14
    Introduction 14 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 15
    Electrical Specifications 2 Electrical Specifications 2.1 2.2 Front Side Bus and GTLREF Most Intel® Xeon® Processor 7200 Series and 7300 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing
  • Intel BFCBASE | Data Sheet - Page 16
    are provided in Table 2-18 and Table 2-19, respectively. These specifications must be met while also meeting signal integrity requirements as outlined in Table 2-18. The processor utilizes differential clocks. Table 2-1 contains processor core frequency to FSB multipliers and their corresponding
  • Intel BFCBASE | Data Sheet - Page 17
    necessarily committed production frequencies. 3. For valid processor core frequencies, refer to the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Specification Update. 4. The lowest bus ratio supported is 1/6. 2.3.1 Front Side Bus Frequency Select
  • Intel BFCBASE | Data Sheet - Page 18
    specifications have been set such that one voltage regulator can operate with all supported frequencies. Individual processor Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series. The Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor
  • Intel BFCBASE | Data Sheet - Page 19
    expected VID range of the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series. 3. The VID range processor to remain within its specifications. 4. Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific
  • Intel BFCBASE | Data Sheet - Page 20
    2.5 2.6 20 Electrical Specifications Reserved, Unused, or Test Signals All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section
  • Intel BFCBASE | Data Sheet - Page 21
    Electrical Specifications Table 2-4. FSB Signal Groups Signal Group AGTL+ Common Clock Input AGTL+ Common Clock Output AGTL+ Common Clock I/O AGTL+ Source Synchronous I/O Type Signals1 Synchronous to BCLK[1:0]
  • Intel BFCBASE | Data Sheet - Page 22
    and AC specifications. See Section 7 for additional timing requirements for entering and leaving the low power states. 2.8 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor(s) be first
  • Intel BFCBASE | Data Sheet - Page 23
    Electrical Specifications 2.9 Note: Mixing Processors Intel supports and validates multi-processor configurations only in which all processors operate with the same FSB frequency, core frequency, number of cores, and have the same internal cache sizes. Mixing components operating at different
  • Intel BFCBASE | Data Sheet - Page 24
    Electrical Specifications 2.11 Processor DC Specifications The following notes apply: • The processor DC specifications in this section are defined at the processor die and not at the package pins unless noted otherwise. • The notes associated with each parameter are part of the specification for
  • Intel BFCBASE | Data Sheet - Page 25
    Motherboard (FMB) guidelines are estimates of the maximum values the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors
  • Intel BFCBASE | Data Sheet - Page 26
    2-9 for further details on the average processor current draw over various time durations. 6. FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See Section 2.11.1 for further details on FMB guidelines. 7. This specification represents the total current for
  • Intel BFCBASE | Data Sheet - Page 27
    specification does not include the current coming from on-board termination (RTT), through the signal line. Refer to the appropriate platform design guide assertion time specification and Table 2-23 for the RESET# Pulse Width specification. Figure 2-1. Quad-Core Intel® Xeon® L7345 Processor Load
  • Intel BFCBASE | Data Sheet - Page 28
    Electrical Specifications Figure 2-2. Dual-Core Dual-Core Intel® Xeon® Processor 7200 Series Load Current versus Time Sustained Current (A) 10 0 95 90 85 80 75 70 65 60 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Figure 2-3. Notes: 1. Processor or Voltage Regulator thermal
  • Intel BFCBASE | Data Sheet - Page 29
    Electrical Specifications Figure 2-4. Quad-Core Intel® Xeon® X7350 Processor Load Current versus Time 13 0 Sustained Current (A) 12 5 12 0 115 110 10 5 10 0 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Notes: 1. Processor or Voltage Regulator thermal protection circuitry should
  • Intel BFCBASE | Data Sheet - Page 30
    overshoot specifications. This table is intended to aid in reading discrete points on Figure 2-5 for Intel® Xeon® Processor 7200 Series and 7300 Series, Figure 2-6 for Intel® Xeon® X7350 Processor , Figure 2-7 for Quad-Core Intel® Xeon® L7345 Processor and Figure 2-8 for Dual-Core Intel
  • Intel BFCBASE | Data Sheet - Page 31
    Electrical Specifications Figure 2-5. Quad-Core Intel® Xeon® Processor 7200 Series and 7300 Series VCC Static and Transient Tolerance Load Lines Vcc [V] and VR implementation. Please refer to the appropriate platform design guide for details on VR implementation. Document Number: 318080-002 31
  • Intel BFCBASE | Data Sheet - Page 32
    Electrical Specifications Figure 2-6. Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance Load Lines 0 V ID - 0.000 Icc guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR implementation. 32 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 33
    Electrical Specifications Figure 2-7. Quad-Core Intel® Xeon® L7345 Processor VCC Static and Transient Tolerance Load Lines 0 VID - 0.000 Icc [A] 5 10 and VR implementation. Please refer to the appropriate platform design guide for details on VR implementation Document Number: 318080-002 33
  • Intel BFCBASE | Data Sheet - Page 34
    Electrical Specifications Figure 2-8. Dual-Core Intel® Xeon® Processor 7200 Series VCC Static and Transient Tolerance Load Lines Vcc [V] refer to the appropriate platform design guide for details on VR implementation. Table 2-11. AGTL+ Signal Group DC Specifications Symbol VIL VIH VOH RON ILI
  • Intel BFCBASE | Data Sheet - Page 35
    Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices. The DualCore Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor Document Number: 318080
  • Intel BFCBASE | Data Sheet - Page 36
    nominal levels will vary between processor families. All PECI devices will operate at the VTT level determined by the processor installed in the system. For specific nominal VTT levels, refer improved noise immunity. Use Figure 2-9 as a guide for input buffer design. 36 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 37
    PECI High Range Maximum VN Minimum VN PECI Ground PECI Low Range Minimum Valid Input Hysteresis Signal Range 2.11.3 VCC Overshoot Specification Processors can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition
  • Intel BFCBASE | Data Sheet - Page 38
    Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. 2.11.4 AGTL+ FSB Specifications Routing topologies are dependent on the processors supported
  • Intel BFCBASE | Data Sheet - Page 39
    VTT on die. Refer to processor I/O Buffer Models for I/V characteristics. 5. COMP resistance must be provided on the system board with +/- 1% resistors. See the applicable platform design guide for implementation details. Table 2-18. FSB Differential BCLK Specifications Symbol VIL VIH VCROSS(abs
  • Intel BFCBASE | Data Sheet - Page 40
    should be used in conjunction with the processor signal integrity models provided by Intel. AGTL+ layout guidelines are also available all specifications in this table apply to all processor frequencies. 2. The processor core clock frequency is derived from BCLK. The bus clock to processor core clock
  • Intel BFCBASE | Data Sheet - Page 41
    synchronous AGTL+ signal timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core (pads). 4. Unless otherwise noted, these specifications apply to both data and address timings. 5. Valid delay timings for these signals are specified
  • Intel BFCBASE | Data Sheet - Page 42
    is required after the assertion and before the deassertion of PROCHOT# for the processor to enable or disable the TCC. 8. Intel recommends the VTT power supply also be removed upon assertion of THERMTRIP#. 9. This specification requires that the VID and BSEL signals be sampled no earlier than 10
  • Intel BFCBASE | Data Sheet - Page 43
    to the falling edge of TCK. 6. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor. 7. Specification for a minimum swing defined between TAP Vt- to Vt+. This assumes a minimum edge rate of 0.5 V/ns. 8. It is recommended that TMS be asserted
  • Intel BFCBASE | Data Sheet - Page 44
    Regulator-Down (EVRD) 11.0 Design Guidelines for addition information. 2. Platform support for VID transitions is required for the processor to operate within specifications. Table 2-26. SMBus Signal Group AC Specifications T# Parameter Min Max Unit Figure Notes 1, 2 T90: SM_CLK Frequency 10
  • Intel BFCBASE | Data Sheet - Page 45
    , and GTLREF_ADD_END at the processor core (pads). 3. All AC processor pins. 6. All AC timings for the SMBus signals are referenced to the SM_CLK at 0.5 * SM_VCC at the processor pins. All SMBus signal timings (SM_DAT, SM_CLK, etc.) are referenced at The circuit used to test the AC specification
  • Intel BFCBASE | Data Sheet - Page 46
    Figure 2-11. Electrical Test Circuit Electrical Specifications Figure 2-12. TCK Clock Waveform TCK V1 V2 V3 Tp Tp = T55: Period V1, V2: For rise and fall times, TCK is measured between 20% and 80% points on the waveform. V3: TCK is referenced to 0.5 * VTT 46 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 47
    Tp Tp = T1: BCLK[1:0] period Ringback Margin Overshoot VH Rising Edge Ringback Falling Edge Ringback, VL Undershoot Figure 2-14. Differential Clock Crosspoint Specification Crossing Point (mV) 650 600 550 500 550 + 0.5 (VHavg - 700) 450 550 mV 400 250 + 0.5 (VHavg - 700) 350 300 250 mV 250
  • Intel BFCBASE | Data Sheet - Page 48
    Figure 2-15. BCLK Waveform at Processor Pad and Pin Electrical Specifications Notes: 1. Waveform at pin is non-monotonic. Waveform at pad is monotonic. 2. Differential Edge Rate (DER) measured zero +/- 200mv. 3. g indicates V/ns units and meg indicates
  • Intel BFCBASE | Data Sheet - Page 49
    Electrical Specifications Figure 2-17. FSB Source Synchronous 2X (Address) Timing Waveform T0 BCLK1 BCLK0 ADSTB# (@ driver) Tp/4 Tp/2 3Tp/4 T1 TR A# (@ driver) TH TJ valid TH TJ
  • Intel BFCBASE | Data Sheet - Page 50
    Electrical Specifications Figure 2-18. FSB Source Synchronous 4X (Data) Timing Waveform T0 BCLK1 Tp/4 Tp/2 3Tp/4 T1 BCLK0 TD DSTBp# (@ driver) DSTBn# (@ driver) D# (@ driver) TA TB TA
  • Intel BFCBASE | Data Sheet - Page 51
    Setup Time Th = T57: TDI, TMS Hold Time V = 0.5 * VTT Note: Please refer to Table 2-12 for TAP Signal Group DC specifications and Table 2-24 for TAP Signal Group AC specifications. Figure 2-20. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform V Tq T q = T59 (TRST# Pulse Width
  • Intel BFCBASE | Data Sheet - Page 52
    Electrical Specifications Figure 2-22. SMBus Timing Waveform t tLOW R tF Clk t HD;STA t HD;STA t HD;DAT t HIGH t t SU;DAT SU;STA Data t BUF P STOP S START S START t LOW =
  • Intel BFCBASE | Data Sheet - Page 53
    Electrical Specifications Figure 2-24. Voltage Sequence Timing Requirements VID[6:1] / BSEL[2:0] VTT VCCPLL Vcc Tc VCC_BOOT Ta Tb Tg Te PWRGOOD BCLK Tf Td Th Reset Configuration Signals(A[
  • Intel BFCBASE | Data Sheet - Page 54
    Electrical Specifications Figure 2-25. FERR#/PBE# Valid Delay Timing BCLK System bus SG Ack STPCLK# FERR#/PBE# FERR# undefined PBE# Ta undefined FERR# Notes: 1. Ta = T40 (FERR#
  • Intel BFCBASE | Data Sheet - Page 55
    Electrical Specifications Figure 2-27. VID Step Times and Vcc Waveforms Ta VID n VCC(max) VCC(min) Tb n-6 to Valid VCC(min) Note: This waveform illustrates an example of an Intel Thermal Monitor 2 transition or an Intel Enhanced SpeedStep Technology transition that is six VID steps down from the
  • Intel BFCBASE | Data Sheet - Page 56
    Electrical Specifications 56 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 57
    Mechanical Specifications 3 Mechanical Specifications The Intel® Xeon® Processor 7200 Series and 7300 Series is packaged in a FC-mPGA6 package that interfaces with the motherboard via a mPGA604 socket. The package consists of two processor dies mounted on a substrate pin-carrier. An IHS is attached
  • Intel BFCBASE | Data Sheet - Page 58
    Figure 3-2.Processor Package Drawing (Sheet 1 of 2) Mechanical Specifications 58 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 59
    Mechanical Specifications Figure 3-3.Processor Package Drawing (Sheet 2 of 2) Document Number: 318080-002 59
  • Intel BFCBASE | Data Sheet - Page 60
    3.2 Mechanical Specifications Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones.
  • Intel BFCBASE | Data Sheet - Page 61
    Mechanical Specifications Figure 3-4.Top Side Board Keepout Zones (Part 1) Document Number: 318080-002 61
  • Intel BFCBASE | Data Sheet - Page 62
    Figure 3-5.Top Side Board Keepout Zones (Part 2) Mechanical Specifications 62 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 63
    Mechanical Specifications Figure 3-6.Bottom Side Board Keepout Zones Document Number: 318080-002 63
  • Intel BFCBASE | Data Sheet - Page 64
    Figure 3-7.Board Mounting-Hole Keepout Zones Mechanical Specifications 64 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 65
    Mechanical Specifications Figure 3-8.Volumetric Height Keep-Ins Document Number: 318080-002 65
  • Intel BFCBASE | Data Sheet - Page 66
    of the processor socket. 4. This specification applies for thermal retention solutions that allow baseboard deflection. 5. This specification applies either for thermal retention solutions that prevent baseboard deflection or for the Intel enabled reference
  • Intel BFCBASE | Data Sheet - Page 67
    is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface. 3.5 Package Insertion Specifications The Intel® Xeon® Processor 7200 Series and 7300 Series can be inserted into and removed from a mPGA604 socket 15 times. The socket should meet the mPGA604
  • Intel BFCBASE | Data Sheet - Page 68
    Mechanical Specifications 3.8 Processor Markings Figure 3-9 shows the topside markings and Figure 3-10 shows the bottom-side markings on the processor. These diagrams are to aid in the identification of the Intel® Xeon® Processor 7200 Series and 7300 Series. Please note that the figures in this
  • Intel BFCBASE | Data Sheet - Page 69
    Mechanical Specifications 3.9 Processor Pin-Out Coordinates Figure 3-11 shows the top view of the processor pin coordinates. The coordinates are referred to throughout the document to identify processor pins. Figure 3-11. Processor Pin-Out Coordinates, Top View Vcc/Vss Vcc/Vss COMMON CLOCK 1
  • Intel BFCBASE | Data Sheet - Page 70
    Mechanical Specifications 70 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 71
    2.6 contains the front side bus signal groups for the Intel® Xeon® Processor 7200 Series and 7300 Series (see Table 2-4). This section provides a sorted pin lists in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor pins ordered alphabetically by pin name. Table 4-2 is a listing
  • Intel BFCBASE | Data Sheet - Page 72
    Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 3 of 16) Pin Name BPMb3# BPRI# BR0# BR1# BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# Pin No. Signal Buffer
  • Intel BFCBASE | Data Sheet - Page 73
    Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 5 of 16) Pin Name Pin No. Signal Buffer Type Direction DEFER# C23 DP0# AC18 DP1# AE19 DP2# AC15 DP3# AE17 DRDY# E18 DSTBN0# Y21 DSTBN1# Y18 DSTBN2# Y15 DSTBN3# Y12 DSTBP0# Y20 DSTBP1# Y17 DSTBP2# Y14 DSTBP3# Y11
  • Intel BFCBASE | Data Sheet - Page 74
    Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 7 of 16) Pin Name SM_WP SMI# STPCLK# TCK TDI TDO TESTHI0 TESTHI1 TESTIN1 TESTIN2 THERMTRIP# TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin No. Signal Buffer Type
  • Intel BFCBASE | Data Sheet - Page 75
    Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 9 of 16) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin No. Signal Buffer Type M1 M3 M5 M7 M9 M23 M25 M27 M29 M31
  • Intel BFCBASE | Data Sheet - Page 76
    Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 11 of 16) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPLL VCC_SENSE VCC_SENSE2 VID1 VID2 VID3 VID4 VID5 VID6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin No. Signal Buffer Type Direction
  • Intel BFCBASE | Data Sheet - Page 77
    Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 13 of 16) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin No. Signal Buffer Type J9 J23 J25 J27 J29 J31 K2 K4 K6 K8
  • Intel BFCBASE | Data Sheet - Page 78
    Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 15 of 16) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin No. Signal Buffer Type V9 V23 V25 V27 V29 V31 W2 W4 W24 W26 W28 W30 Y1 Y3
  • Intel BFCBASE | Data Sheet - Page 79
    Pin Listing 4.1.2 Pin Listing by Pin Number Table 4-2. Pin Listing by Pin Number (Sheet 1 of 14) Pin No. Pin Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 VID5 VTT_SEL SKTOCC# VTT VSS
  • Intel BFCBASE | Data Sheet - Page 80
    Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 3 of 14) Pin No. Pin Name C23 C24 C25 C26 C27 C28 C29 C30 C31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 E1 E2 E3 E4 DEFER# TDI VSS IGNNE# SMI# PECI VSS VCC Reserved
  • Intel BFCBASE | Data Sheet - Page 81
    Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 5 of 14) Pin No. Pin Name Signal Buffer Type Direction F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 G1 G2 G3 G4 G5 G6 G7 G8 G9 G23 G24 G25 G26 G27 G28 G29 G30 G31 H1 H2 H3 H4 H5 H6 H7 H8 H9 H23 H24 H25 DBSY# VSS BNR# RS2# A37#
  • Intel BFCBASE | Data Sheet - Page 82
    Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 7 of 14) Pin No. Pin Name L3 VSS L4 VCC L5 VSS L6 VCC L7 VSS L8 VCC L9 VSS L23 VSS L24 VCC L25 VSS L26 VCC L27 VSS L28 VCC L29 VSS L30 VCC L31 VSS M1 VCC M2 VSS M3 VCC M4 VSS M5 VCC M6 VSS M7 VCC M8 VSS
  • Intel BFCBASE | Data Sheet - Page 83
    Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 9 of 14) Pin No. Pin Name T1 VSS T2 VCC T3 VSS T4 VCC T5 VSS T6 VCC T7 VSS T8 VCC T9 VSS T23 VSS T24 VCC T25 VSS T26 VCC T27 VSS T28 VCC T29 VSS T30 VCC T31 VSS U1 VCC U2 VSS U3 VCC U4 VSS U5 VCC U6 VSS
  • Intel BFCBASE | Data Sheet - Page 84
    Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 11 of 14) Pin No. Pin Name Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 DSTBP1# DSTBN1#
  • Intel BFCBASE | Data Sheet - Page 85
    Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 13 of 14) Pin No. Pin Name AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 D41# VSS D50# DP2#
  • Intel BFCBASE | Data Sheet - Page 86
    Pin Listing 86 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 87
    processor's address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction to the appropriate pins on all Intel® Xeon® Processor 7200 Series and 7300 Series
  • Intel BFCBASE | Data Sheet - Page 88
    transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock edges. BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters
  • Intel BFCBASE | Data Sheet - Page 89
    :0]# D[31:16]# D[47:32]# D[63:48]# DBSY# DEFER# DP[3:0]# DRDY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate
  • Intel BFCBASE | Data Sheet - Page 90
    functionality, including the identification of support of the feature and enable/disable information, refer to Vol. 3 of the IA_32 Intel ® Architecture Software Developer's Manual and the AP-485 Intel® Processor Identification and the CPUID Instruction application note. I The FORCEPR# (force
  • Intel BFCBASE | Data Sheet - Page 91
    recognition of this signal following an I/O write instruction, it must be valid along with the Intel®64 and IA32 Architectures Software Developer's Manual, Volume 3: System Programming Guide. PECI is a proprietary one-wire bus interface that provides a communication channel between Intel processor
  • Intel BFCBASE | Data Sheet - Page 92
    pulse width specification in Table 2-16, and be followed by a 1-10 ms RESET# pulse. The PWRGOOD signal must be supplied to the processor; it is of these signals. SM_VCC provides power to the SMBus components on the Intel® Xeon® Processor 7200 Series and 7300 Series package. WP (Write Protect) can be
  • Intel BFCBASE | Data Sheet - Page 93
    #, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. See the XDP: Debug Port Design Guide for Intel® 7300 Chipset
  • Intel BFCBASE | Data Sheet - Page 94
    support processor voltage specification processor core power and ground. These signals should be used to provide feedback to the voltage regulator signals, which ensure the output voltage (that is, processor voltage) remains within specification. Please see the applicable platform design guide
  • Intel BFCBASE | Data Sheet - Page 95
    , refer to the DualCore Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide. Thermal Specifications To allow the optimal operation and long-term reliability of Intel processor-based systems, the processor must remain within the
  • Intel BFCBASE | Data Sheet - Page 96
    Motherboard (FMB) guidelines, even if a processor with lower power dissipation is currently planned. Thermal Monitor and Thermal Monitor 2 feature must be enabled for the processor to remain within its specifications. Table 6-1. Quad-Core Intel® Xeon® E7300 Processor Thermal Specifications Core
  • Intel BFCBASE | Data Sheet - Page 97
    in a future release of this document. 5. Power specifications are defined at all VIDs found in Table 2-3. The Quad-Core Intel® Xeon® E7300 Processor may be shipped under multiple VIDs for each frequency. 6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned
  • Intel BFCBASE | Data Sheet - Page 98
    specifications are defined at all VIDs found in Table 2-3. The Intel® Xeon® X7350 Processor may be shipped under multiple VIDs for each frequency. 6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Figure 6-2.Quad-Core Intel
  • Intel BFCBASE | Data Sheet - Page 99
    as more characterization data becomes available. 5. Power specifications are defined at all VIDs found in Table 2-3. The Quad-Core Intel® Xeon® L7345 Processor may be shipped under multiple VIDs for each frequency. 6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all
  • Intel BFCBASE | Data Sheet - Page 100
    Specifications Figure 6-3. Quad-Core Intel® Xeon® L7345 Processor Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide for system and environmental implementation details. Table 6-6. Quad-Core Intel® Xeon® L7345 Processor
  • Intel BFCBASE | Data Sheet - Page 101
    in a future release of this document. 5. Power specifications are defined at all VIDs found in Table 2-3. The Dual-Core Intel® Xeon® Processor 7200 Series may be shipped under multiple VIDs for each frequency. 6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all
  • Intel BFCBASE | Data Sheet - Page 102
    in a future release of this document. 5. Power specifications are defined at all VIDs found in Table 2-3. The Dual-Core Intel® Xeon® Processor 7200 Series may be shipped under multiple VIDs for each frequency. 6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all
  • Intel BFCBASE | Data Sheet - Page 103
    Thermal Monitor Features The Intel® Xeon® Processor 7200 Series and 7300 Series provide two thermal monitor features, Thermal Monitor (TM1) and Enhanced Thermal Monitor (TM2). The TM1 and TM2 must both be enabled in BIOS for the processor to be operating within specifications. When both are enabled
  • Intel BFCBASE | Data Sheet - Page 104
    Enhanced Thermal Monitor must be enabled for the processor to be operating within specifications. TM2 requires support for dynamic VID transitions in the platform. Not all Intel® Xeon® Processor 7200 Series and 7300 Series are capable of supporting TM2. When Thermal Monitor 2 is enabled, and a high
  • Intel BFCBASE | Data Sheet - Page 105
    Thermal Specifications to reach the target operating voltage. Each step will be one VID table entry (see Table 2-3). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of
  • Intel BFCBASE | Data Sheet - Page 106
    to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. Refer to the Intel®64 and IA-32 Architectures Software Developer's Manual. PROCHOT# is designed to
  • Intel BFCBASE | Data Sheet - Page 107
    Thermal Specifications 6.3 Platform Environment Control Interface (PECI) 6.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 6-7 shows an example of the PECI
  • Intel BFCBASE | Data Sheet - Page 108
    rate and alpha-beta filter may have no effect on the fan control algorithm. PECI Specifications PECI Device Address The Intel® Xeon® Processor 7200 Series and 7300 Series obtains its PECI address based on the processor APIC ID[4:2] at power on. APIC ID[4:3] is also known as Cluster ID[1:0] and APIC
  • Intel BFCBASE | Data Sheet - Page 109
    Thermal Specifications Table 6-9. BREQ# signal assertion during power on BREQ0# Asserted Asserted Not asserted Not asserted BREQ1# Not asserted Asserted Asserted Not asserted AgentID[1:0] Die 0 00 10 AgentID[1:0] Die 1 01 11 This combination is not supported by the processor Table 6-10 shows
  • Intel BFCBASE | Data Sheet - Page 110
    Specifications Prior to a power on RESET# and during RESET# assertion, PECI is not guaranteed to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor () Error Code Support The error codes supported for the processor GetTemp0() and
  • Intel BFCBASE | Data Sheet - Page 111
    the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the Intel® Xeon® Processor 7200 Series and 7300 Series package.. 7.2 Clock Control and Low Power States The Intel® Xeon® Processor 7200 Series and 7300 Series supports the Extended
  • Intel BFCBASE | Data Sheet - Page 112
    its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. HALT State HALT is a low power state entered when the processor has executed the HALT or MWAIT instruction. When one of the processor cores executes the HALT or MWAIT instruction, that processor
  • Intel BFCBASE | Data Sheet - Page 113
    running in HALT state. 2. This specification is characterized by design. 3. Processors running in the lowest bus ratio will enter the HALT state when the processor has executed the HALT and MWAIT instruction since the processor is already in the lowest core frequency and voltage operating point. The
  • Intel BFCBASE | Data Sheet - Page 114
    State Machine Normal State Normal execution HALT or MWAIT Instruction and HALT Bus Cycle Generated INIT#, BINIT#, INTR, once the processor is in the Stop Grant state. All processor cores will enter the StopGrant state once the STPCLK# pin is asserted. Additionally, all processor cores must be
  • Intel BFCBASE | Data Sheet - Page 115
    and 7300 Series may be capable of supporting Enhanced Intel SpeedStep Technology. More details on which processor frequencies will support this feature will be provided in future releases of the Intel® Xeon® Processor 7200, 7300 Series Specification Update when available. Document Number: 318080
  • Intel BFCBASE | Data Sheet - Page 116
    are key features of Enhanced Intel SpeedStep Technology: • Multiple voltage/frequency operating points provide optimal performance at reduced power consumption. • Voltage/frequency selection is software controlled by writing to processor MSR's (Model Specific Registers), thus eliminating chipset
  • Intel BFCBASE | Data Sheet - Page 117
    on the processor substrate to ensure that the memory components are in a known state in systems which do not support the SMBus (or only support a partial implementation address inputs may cause address recognition problems. Refer to the appropriate platform design guide document. Figure 7-2 shows a
  • Intel BFCBASE | Data Sheet - Page 118
    bit 2 0 0 1 1 0 0 1 1 SM_EP_A0 bit 1 0 1 0 1 0 1 0 1 Note: 1. This addressing scheme will support up to 8 processors on a single SMBus. R/W bit 0 X X X X X X X X 7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM (PIROM) responds to two SMBus packet types
  • Intel BFCBASE | Data Sheet - Page 119
    05h 8 06h 8 07h 8 08h 8 09h 8 0Ah 8 0B - 0Ch 16 0Dh 8 Processor Data: 0E - 13h 48 14h 6 2 15h 8 Processor Core Data: 16 - 19h 2 8 4 Function Data Format Revision PIROM Size Processor Data Address Processor Core Data Address L3 Cache Data Address Package Data Address Part
  • Intel BFCBASE | Data Sheet - Page 120
    Data: 74 - 77h 32 Function Notes Reserved Processor Core Type Processor Core Family Processor Core Model Processor Core Stepping Reserved Front Side Bus Speed Multiprocessor Support Reserved Maximum Core Frequency Maximum Core VID Minimum Core Voltage TCASE Maximum Checksum Reserved for future
  • Intel BFCBASE | Data Sheet - Page 121
    Present [3] = Reserved [2] = OEM EEPROM Present [1] = Core VID Present [0] = L3 Cache Present Processor Thread and Core [7:2] = Number of cores Information [1:0] = Number of threads per core Additional Processor Feature Flags [7] = Reserved [6] = Intel® Cache Safe Technology [5] = Extended Halt
  • Intel BFCBASE | Data Sheet - Page 122
    to this register have no effect. 7.4.3.1.5 Offset: 04h Bit Description 7:0 Processor Core Data Address Byte pointer to the Processor Data section 00h: Processor Core Data section not present 01h - 15h: Reserved 16h: Processor Core Data section pointer value 17h-FFh: Reserved L3CDA: L3 Cache
  • Intel BFCBASE | Data Sheet - Page 123
    Features 7.4.3.1.6 PDA: Package Data Address This location provides the offset to the Package Data Section. Writes to this register have no effect. 7.4.3.1.7 Offset: 06h Bit Description 7:0 Package Data Address Byte pointer to the Package Data section 00h: Package Data section not present
  • Intel BFCBASE | Data Sheet - Page 124
    Features 7.4.3.1.9 FDA: Feature Data Address This location provides the offset to the Feature Data Section. Writes to this register have no effect. Offset: 09h Bit Description 7:0 Feature Data Address Byte pointer to the Feature Data section 00h: Feature Data section not present 01h - 73h:
  • Intel BFCBASE | Data Sheet - Page 125
    the value is less than six characters in length, leading spaces (20h) are programmed in this field. Writes to this register have no effect. Example: A processor with a S-Spec mark of SLA67 contains the following in field 0E13h: 20h, 53h, 4Ch, 41h, 36h, 37h. This data consists of one blank at 0Eh
  • Intel BFCBASE | Data Sheet - Page 126
    Processor Core Data This section contains core silicon-related data. CPUID: CPUID This location contains the CPUID, Processor Type, Family, Model and Stepping. The CPUID field is a copy of the results in EAX[27:0] from Function 1 of the CPUID instruction stepping Intel® Xeon® Processor 7200 Series
  • Intel BFCBASE | Data Sheet - Page 127
    provided is the speed, rounded to a whole number, and reflected in hex. Writes to this register have no effect. Example: The Intel® Xeon® Processor 7200 Series and 7300 Series supports a 1066 MTS front side bus. Therefore, offset 1A - 1Bh has a value of 042Ah. Offset: 1Ah-1Bh Bit 15:0 Front Side
  • Intel BFCBASE | Data Sheet - Page 128
    supported number of physical processors on the bus. These two bits are MSB aligned where 00b equates to singleprocessor operation, 01b is a dual-processor operation, and 11b represents multiprocessor operation. The Intel® Xeon® Processor maximum core VID would contain 0546h (1350 decimal) in Offset 1F -
  • Intel BFCBASE | Data Sheet - Page 129
    Bit 15:0 Minimum Core Voltage 0000h-FFFFh: mV Description 7.4.3.3.7 TCASE: TCASE Maximum This location provides the maximum TCASE for the processor. The field reflects temperature in degrees Celsius in hex format. This data can be found in Section 6. The thermal specifications are specified at
  • Intel BFCBASE | Data Sheet - Page 130
    Cache Size This location contains the size of the level three cache in kilobytes. Writes to this register have no effect. Example: The Intel® Xeon® Processor 7200 Series and 7300 Series has no L3 cache. Thus, offset 29 - 2Ah will contain 0000h (0 decimal). 7.4.3.4.4 Offset: 29h-2Ah Bit 15:0 L3
  • Intel BFCBASE | Data Sheet - Page 131
    ). The package is documented as 1.0, 2.0, etc. If this only consumes three ASCII characters, a leading space is provided in the data field. Example: The Intel® Xeon® Processor 7200 Series and 7300 Series utilizes the first revision of the FC-mPGA6 package. Thus, at offset 32-35h, the data is a space
  • Intel BFCBASE | Data Sheet - Page 132
    reflecting the Intel part number for the processor. This information is typically marked on the outside of the processor. If the part number is less than 7 characters, a leading space is inserted into the value. The part number should match the information found in the marking specification found in
  • Intel BFCBASE | Data Sheet - Page 133
    in this field is either a serial signature or an electronic signature. Bits 5 & 6 of the Processor Feature Flags (Offset 78h) indicates which signature is present. Intel does not guarantee that each processor will have a unique value in this field. Writes to this register have no effect. Offset
  • Intel BFCBASE | Data Sheet - Page 134
    Features 7.4.3.6.4 RES7: Reserved 7 This location is reserved. Writes to this register have no effect. 7.4.3.6.5 Offset: 55h-6Eh Bit 207:0 RESERVED 7 Description PNDCKS: Part Number Data Checksum This location provides the checksum of the Part Number Data Section. Writes to this register
  • Intel BFCBASE | Data Sheet - Page 135
    on the processor. Processor Core Feature Flags This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID instruction. These details provide instruction and feature support by product family. A decode of these bits is found in the AP-485 Intel® Processor Identification and
  • Intel BFCBASE | Data Sheet - Page 136
    cores 1:0 Number of threads per core Description Additional Processor Feature Flags This location contains additional feature information for the processor. This field is defined as follows: Writes to this register have no effect. 7.4.3.8.5 Offset: 7Ah Bit Description 7 Reserved 6 Intel
  • Intel BFCBASE | Data Sheet - Page 137
    Data Processor Core Data Cache Data Package Data Part Number Data Thermal Ref. Data Feature Data Checksum Address 0Dh 15h 24h 31h 37h 6Fh 73h 7Fh Checksums are automatically calculated and programmed by Intel. The first step in calculating the checksum is to add each byte from the field to
  • Intel BFCBASE | Data Sheet - Page 138
    Features 138 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 139
    Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 8.2 8.2.1 Introduction The Intel® Xeon® Processor 7200 Series and 7300 Series is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard
  • Intel BFCBASE | Data Sheet - Page 140
    Boxed Processor Specifications 140 Document Number: 318080-002
  • Intel BFCBASE | Data Sheet - Page 141
    information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Intel® Xeon® Processor 7200 Series and 7300 Series-based multiprocessor systems, the LAI is critical in
  • Intel BFCBASE | Data Sheet - Page 142
    Debug Tools Specifications 9.2.2 Electrical Considerations The LAI will also affect the electrical performance of the FSB will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide. § 142 Document Number: 318080-002
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Document Number:
318080-002
Notice:
The Intel
®
Xeon
®
Processor 7200 Series and 7300 Series may contain design defects or errors known
as errata which may cause the product to deviate from published specifications. Current characterized errata are
available on request.
Intel
®
Xeon
®
Processor 7200 Series
and 7300 Series
Datasheet
September 2008