Intel BFCBASE Data Sheet - Page 108
PECI Specifications
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Thermal Specifications Figure 6-8. Conceptual Fan Control Diagram For a PECI-Based Platform Fan Speed (RPM) Min TCONTROL Setting Max PECI = -10 TCC Activation Temperature PECI = 0 PECI = -20 Temperature (not intended to depict actual implementation) 6.3.1.2 6.3.2 6.3.2.1 Processor Thermal Data Sample Rate and Filtering The DTS (Digital Thermal Sensors) provide an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals. The DTS sample interval range can be modified, and a data filtering algorithm can be activated to help moderate this. The DTS sample interval range is 82 us (default) to 20 ms (max). This value can be set in BIOS. To reduce the sample rate requirements on PECI and improve thermal data stability vs. time the processor DTS also implements an averaging algorithm that filters the incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) + (new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on by default and can be turned off in BIOS. Host controllers should utilize the min/max sample times to determine the appropriate sample rate based on the controller's fan control algorithm and targeted response rate. The key items to take into account when settling on a fan control algorithm are the DTS sample rate, whether the temperature filter is enabled, how often the PECI host will poll the processor for temperature data, and the rate at which fan speed is changed. Depending on the designer's specific requirements the DTS sample rate and alpha-beta filter may have no effect on the fan control algorithm. PECI Specifications PECI Device Address The Intel® Xeon® Processor 7200 Series and 7300 Series obtains its PECI address based on the processor APIC ID[4:2] at power on. APIC ID[4:3] is also known as Cluster ID[1:0] and APIC ID[2] is also known as Agent ID[1]. Cluster ID[1:0] is set by the chipset driven power-on configuration (POC) signals A[12:11]#. Table 6-9 shows how the Agent ID is generated for each of the die based on the BREQ# signals asserted during power on for the Intel® Xeon® Processor 7200 Series and 7300 Series. 108 Document Number: 318080-002