Intel BFCBASE Data Sheet - Page 135

Features 7.4.3.8 7.4.3.8.1 Feature Data This section provides information on key features that the platform may need to understand without powering on the processor. Processor Core Feature Flags This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID instruction. These details provide instruction and feature support by product family. A decode of these bits is found in the AP-485 Intel® Processor Identification and CPUID Instruction application note. Writes to this register have no effect. Example: A value of BFEBFBFFh can be found at offset 74 - 77h. 7.4.3.8.2 Note: Offset: 74h-77h Bit 31:0 Description Processor Core Feature Flags 0000h-FFFFF: Feature Flags Processor Feature Flags This location contains additional feature information from the processor. Writes to this register have no effect. Bit 5 and Bit 6 are mutually exclusive (only one bit will be set). 7.4.3.8.3 Offset: 78h Bit Description 7 Multi-Core (set if the processor is a multi core processor) 6 Serial signature (set if there is a serial signature at offset 4D - 54h) 5 Electronic signature present (set if there is a electronic signature at 4D - 54h) 4 Thermal Sense Device present (set if an SMBus thermal sensor on package) 3 Reserved 2 OEM EEPROM present (set if there is a scratch ROM at offset 80 - FFh) 1 Core VID present (set if there is a VID provided by the processor) 0 L3 Cache present (set if there is a level 3 cache on the processor) Bits are set when a feature is present, and cleared when they are not. Example: A value of A6h can be found at offset 78h. Processor Thread and Core Information This location contains information regarding the number of cores and threads on the processor. Writes to this register have no effect. Example: The Intel® Xeon® Processor 7200 Series and 7300 Series has two or four cores and one thread per core. Document Number: 318080-002 135