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Intel BFCBASE Data Sheet - Page 129

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Features 7.4.3.3.6 Note: MINV: Minimum Core Voltage This location contains the minimum Processor Core voltage. This field, rounded to the next thousandth, is in mV and is reflected in hex. The minimum VCC reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw. Writes to this register have no effect. The minimum core voltage value in offset 21 - 22h is a single value that assumes the FMB maximum current draw. Refer to Table 2-10 and Table 2-11 for the minimum core voltage specifications based on actual real-time current draw. Example: A voltage of 1.000 V minimum core voltage would contain 03E8h (1000 decimal) in Offset 21 - 22h. Offset: 21h-22h Bit 15:0 Minimum Core Voltage 0000h-FFFFh: mV Description 7.4.3.3.7 TCASE: TCASE Maximum This location provides the maximum TCASE for the processor. The field reflects temperature in degrees Celsius in hex format. This data can be found in Section 6. The thermal specifications are specified at the case Integrated Heat Spreader (IHS).Writes to this register have no effect. Example: A temperature of 66C would contain 42h (66 decimal) in Offset 23h. 7.4.3.3.8 Offset: 23h Bit 7:0 TCASE Maximum 00h-FFh: Degrees Celsius Description PCDCKS: Processor Core Data Checksum This location provides the checksum of the Processor Core Data Section. Writes to this register have no effect. 7.4.3.4 Offset: 24h Bit Description 7:0 Processor Core Data Checksum One Byte Checksum of the Processor Core Data Section 00h- FFh: See Section 7.4.4 for calculation of the value Cache Data This section contains cache-related data. Document Number: 318080-002 129

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141