Intel BFCBASE Data Sheet - Page 43
Table 2-24., TAP Signal Group AC Specifications Sheet 2 of 2
UPC - 735858197373
View all Intel BFCBASE manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 43 highlights
Electrical Specifications Table 2-24. TAP Signal Group AC Specifications (Sheet 2 of 2) T# Parameter T57: TDI, TMS Hold Time T58: TDO Clock to Output Delay T59: TRST# Assert Time Min 7.5 0 2 Max 7.5 Unit ns ns TTCK Figure 2-19 2-19 2-20 Notes 1, 2, 8 4,7 5 6 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3. This specification is based on the capabilities of the ITP debug port, not on processor silicon. 4. Referenced to the rising edge of TCK. 5. Referenced to the falling edge of TCK. 6. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor. 7. Specification for a minimum swing defined between TAP Vt- to Vt+. This assumes a minimum edge rate of 0.5 V/ns. 8. It is recommended that TMS be asserted while TRST# is being deasserted. Document Number: 318080-002 43