Intel BFCBASE Data Sheet - Page 20
Reserved, Unused, or Test Signals, 2.6 Front Side Bus Signal Groups, Table 2-24
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2.5 2.6 20 Electrical Specifications Reserved, Unused, or Test Signals All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 4 for a pin listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active high inputs, should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected; however, this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the baseboard trace for FSB signals, unless otherwise noticed in the appropriate platform design guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (RTT). For details see Table 2-24. TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include ondie termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. Signal termination for these signal types is discussed in the appropriate platform design guidelines. For each processor socket, connect the TESTIN1 and TESTIN2 signals together, then terminate the net with a 51 Ω resistor to VTT The TESTHI signal must be tied to the processor VTT using a matched resistor, where a matched resistor has a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω is required. The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group: • TESTHI[1:0] - can be grouped together with a single pull-up to VTT Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active anytime and include an active PMOS pull-up transistor to assist during the first clock of a low-to-high voltage transition. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2-4 identifies which signals are common clock, source synchronous and asynchronous. Document Number: 318080-002