Intel BFCBASE Data Sheet - Page 93

Signal Definitions Table 5-1. Signal Definitions (Sheet 7 of 8) Name SMI# STPCLK# TCK TDI TDO TESTHI[1:0] TESTIN1 TESTIN2 THERMTRIP# TMS TRDY# TRST# VCCPLL VCC_SENSE VCC_SENSE2 Type I I I I O I I I O I I I I O Description Notes SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tri-state its outputs. See Section 7.1. STPCLK# (Stop Clock), when asserted, causes processors to enter a low power StopGrant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TESTHI[1:0] must be connected to a Vtt power source through a resistor for proper processor operation. Refer to Section 2.5 for TESTHI grouping restrictions. TESTIN1 must be connected to a VTT power source through a resistor as well as to the TESTIN2 pin of the same socket for proper processor operation. TESTIN2 must be connected to a VTT power source through a resistor as well as to the TESTIN1 pin of the same socket for proper processor operation. Refer to Section 2.5 for TESTIN restrictions. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed following the assertion of THERMTRIP#. See Figure 2-21 and Table 2-22 for the appropriate power down sequence and timing requirements. Intel also recommends the removal of VTT when THERMTRIP# is asserted. Driving of the THERMTRIP# signals is enabled within 10 μs of the assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated, THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. See the XDP: Debug Port Design Guide for Intel® 7300 Chipset Platforms for further information. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. The Intel® Xeon® Processor 7200 Series and 7300 Series implement an on-die PLL filter solution. The VCCPLL input is used as a PLL supply voltage. VCC_SENSE and VCC_SENSE2 provides an isolated, low impedance connection to the processor core power and ground. These signals should be used to provide feedback to the voltage regulator signals, which ensure the output voltage (that is, processor voltage) remains within specification. Please see the applicable platform design guide for implementation details. Document Number: 318080-002 93