Intel BFCBASE Data Sheet - Page 25

Document Number: 318080-002

25

Electrical Specifications

2.11.1

Flexible Motherboard Guidelines (FMB)

The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the

Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon®

Processor 7300 Series will have over certain time periods. The values are only

estimates and actual specifications for future processors may differ. Processors may or

may not have specifications equal to the FMB value in the foreseeable future. System

designers should meet the FMB values to ensure their systems will be compatible with

future processors.

Table 2-9.

Voltage and Current Specifications

(Sheet 1 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1,17

VID

VID range

1.0000

1.5000

V

V

CC

V

CC

for processor core

Launch - FMB

See

Table 2-10

,

Figure 2-5

,

Figure 2-6

and

Figure 2-7

V

2, 3, 4, 6,

9

V

CC

_

BOOT

Default V

CC

Voltage for initial power up

1.10

V

2

V

VID_STEP

VID step size during a transition

±

12.5

mV

V

VID_SHIFT

Total allowable DC load line shift from

VID steps

450

mV

10

V

TT

FSB termination voltage (DC + AC

specification)

1.14

1.20

1.26

V

8, 13

V

CCPLL

PLL supply voltage (DC + AC

specification)

1.425

1.50

1.605

V

SM_VCC

SMBus supply voltage

3.135

3.300

3.465

V

I

CC

I

CC

for Quad-Core Intel® Xeon® L7345

Processor with multiple VID

Launch - FMB

60

A

4, 5, 6, 9

I

CC_RESET

I

CC_RESET

for Quad-Core Intel® Xeon®

L7345 Processor with multiple VID

Launch - FMB

60

A

17

I

CC

I

CC

for Dual-Core Intel® Xeon®

Processor 7200 Series with multiple

VID

Launch - FMB

90

A

4, 5, 6, 9

I

CC_RESET

I

CC_RESET

for Dual-Core Intel® Xeon®

Processor 7200 Series with multiple

VID

Launch - FMB

90

A

17

I

CC

I

CC

for Intel

®

Xeon

®

Processor 7200

Series and 7300 Series with multiple

VID

Launch - FMB

90

A

4, 5, 6, 9

I

CC_RESET

I

CC_RESET

for Intel

®

Xeon

®

Processor

7200 Series and 7300 Series with

multiple VID

Launch - FMB

90

A

17

I

CC

I

CC

for Intel® Xeon® X7350 Processor

with multiple VID

Launch - FMB

130

A

4, 5, 6, 9

I

CC_RESET

I

CC_RESET

for Intel® Xeon® X7350

Processor

with multiple VID

Launch - FMB

130

A

17

I

SM_VCC

Icc for SMBus supply

100

122.5

mA

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Intel BFCBASE Data Sheet - Page 25

Flexible Motherboard Guidelines (FMB), Table 2-9., Voltage and Current Specifications

Page 25 highlights