Intel BFCBASE Data Sheet - Page 118

PIROM and Scratch EEPROM Supported SMBus Transactions, Table 7-3.

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Features Table 7-3. Memory Device SMBus Addressing Address (Hex) Upper Address1 Device Select A0h/A1h A2h/A3h A4h/A5h A6h/A7h A8h/A9h AAh/ABh ACh/ADh AEh/AFh bits 7-4 1010 1010 1010 1010 1010 1010 1010 1010 SM_EP_A2 bit 3 0 0 0 0 1 1 1 1 SM_EP_A1 bit 2 0 0 1 1 0 0 1 1 SM_EP_A0 bit 1 0 1 0 1 0 1 0 1 Note: 1. This addressing scheme will support up to 8 processors on a single SMBus. R/W bit 0 X X X X X X X X 7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM (PIROM) responds to two SMBus packet types: Read Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge a Write Byte command but ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte commands. Table 7-4 diagrams the Read Byte command. Table 7-5 diagrams the Write Byte command. Following a write cycle to the scratch ROM, software must allow a minimum of 10 ms before accessing either ROM of the processor. In the tables, 'S' represents the SMBus start bit, 'P' represents a stop bit, 'R' represents a read bit, 'W' represents a write bit, 'A' represents an acknowledge (ACK), and '///' represents a negative acknowledge (NACK). The shaded bits are transmitted by the Processor Information ROM or Scratch EEPROM, and the bits that aren't shaded are transmitted by the SMBus host controller. In the tables, the data addresses indicate 8 bits. The SMBus host controller should transmit 8 bits with the most significant bit indicating which section of the EEPROM is to be addressed: the Processor Information ROM (MSB = 0) or the Scratch EEPROM (MSB = 1). Table 7-4. Read Byte SMBus Packet Slave S Addres s 1 7-bits Write 1 A Comman d Code A S Slave Address Read A 1 8-bits 11 7-bits 1 1 Data 8-bits /// P 1 1 Table 7-5. Write Byte SMBus Packet S Slave Address 1 7-bits Write 1 A Command Code A 1 8-bits 1 Data 8-bits AP 1 1 118 Document Number: 318080-002

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Features
118
Document Number: 318080-002
Note:
1.
This addressing scheme will support up to 8 processors on a single SMBus.
7.4.2
PIROM and Scratch EEPROM Supported SMBus
Transactions
The Processor Information ROM (PIROM) responds to two SMBus packet types: Read
Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge
a Write Byte command but ignore the data. The Scratch EEPROM responds to Read
Byte and Write Byte commands.
Table 7-4
diagrams the Read Byte command.
Table 7-5
diagrams the Write Byte command. Following a write cycle to the scratch
ROM, software must allow a minimum of 10 ms before accessing either ROM of the
processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents
a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’
represents a negative acknowledge (NACK). The shaded bits are transmitted by the
Processor Information ROM or Scratch EEPROM, and the bits that aren’t shaded are
transmitted by the SMBus host controller. In the tables, the data addresses indicate 8
bits. The SMBus host controller should transmit 8 bits with the most significant bit
indicating which section of the EEPROM is to be addressed: the Processor Information
ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
Table 7-3.
Memory Device SMBus Addressing
Address
(Hex)
Upper
Address
1
Device Select
R/W
bits 7-4
SM_EP_A2
bit 3
SM_EP_A1
bit 2
SM_EP_A0
bit 1
bit 0
A0h/A1h
1010
0
0
0
X
A2h/A3h
1010
0
0
1
X
A4h/A5h
1010
0
1
0
X
A6h/A7h
1010
0
1
1
X
A8h/A9h
1010
1
0
0
X
AAh/ABh
1010
1
0
1
X
ACh/ADh
1010
1
1
0
X
AEh/AFh
1010
1
1
1
X
Table 7-4.
Read Byte SMBus Packet
S
Slave
Addres
s
Write
A
Comman
d Code
A
S
Slave
Address
Read
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Table 7-5.
Write Byte SMBus Packet
S
Slave Address
Write
A
Command Code
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1