Intel BFCBASE Data Sheet - Page 54
VID Step Timings, T84: VID Down to Valid V
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Electrical Specifications Figure 2-25. FERR#/PBE# Valid Delay Timing BCLK System bus SG Ack STPCLK# FERR#/PBE# FERR# undefined PBE# Ta undefined FERR# Notes: 1. Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion). 2. FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions, the PBE# signal is driven. FERR# is driven at all other times. Figure 2-26. VID Step Timings VID n VCC(max) Tb VCC(min) n-1 ... Ta m m+1 Tc Td Ta = T84: VID Down to Valid VCC(max) Tb = T82: VID Down to Valid VCC(min) Tc = T85: VID Up to Valid VCC(max) Td = T83: VID Up to Valid VCC(min) 54 Document Number: 318080-002
Electrical Specifications
54
Document Number: 318080-002
Notes:
1.
Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion).
2.
FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the
FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined
regions, the PBE# signal is driven. FERR# is driven at all other times.
Figure 2-25. FERR#/PBE# Valid Delay Timing
BCLK
STPCLK#
System bus
FERR#/PBE#
SG
Ack
FERR#
undefined
FERR#
Ta
PBE#
undefined
Figure 2-26. VID Step Timings
VID
n
n-1
m+1
m
...
Ta
Tb
Tc
Td
Ta
=
T84: VID Down to Valid V
CC
(max)
Tb
=
T82: VID Down to Valid V
CC
(min)
Tc
=
T85: VID Up to Valid V
CC
(max)
Td
=
T83: VID Up to Valid V
CC
(min)
V
CC
(max)
V
CC
(min)