Intel BFCBASE Data Sheet - Page 22

Electrical Specifications

22

Document Number: 318080-002

Table 2-5

outlines the signals which include on-die termination (R

TT

).

Table 2-6

outlines non AGTL+ signals including open drain signals.

Table 2-7

provides signal

reference voltages.

Note:

1.

Signals that have RTT in the package with 50

Ω

pullup to V

TT

.

2.7

CMOS Asynchronous and Open Drain

Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize

CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,

THERMTRIP#, and TDO utilize open drain output buffers. All of the CMOS and Open

Drain signals are required to be asserted/deasserted for at least eight BCLKs in order

for the processor to recognize the proper signal state. See

Section 2.11

and

Section 2.12

for the DC and AC specifications. See

Section 7

for additional timing

requirements for entering and leaving the low power states.

2.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, it is recommended that the processor(s) be first in the TAP chain and followed by

any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of

accepting an input of the appropriate voltage. Similar considerations must be made for

TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a

different voltage level.

Table 2-5.

AGTL+ Signal Description Table

AGTL+ signals with R

TT

1

AGTL+ signals with no R

TT

A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,

BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,

DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,

REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

BPM[5:0]#, BPMb[3:0]#, RESET#, BR[1:0]

Table 2-6.

Non AGTL+ Signal Description Table

Signals with R

TT

Signals with no R

TT

A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0],

FERR#/PBE#, FORCEPR#, GTLREF_ADD_MID,

GTLREF_ADD_END, GTLREF_DATA_MID,

GTLREF_DATA_END, IERR#, IGNNE#, INIT#,

LINT0/INTR, LINT1/NMI, LL_ID[1:0], PROC_ID[1:0],

PECI, PROCHOT#, PWRGOOD, SKTOCC#, SMI#,

STPCLK#, TCK, TDI, TDO, TESTHI[1:0], TESTIN1,

TESTIN2, THERMTRIP#, TMS, TRST#, VCC_SENSE,

VCC_SENSE2, VID[6:1], VSS_SENSE, VSS_SENSE2,

VTT_SEL

Table 2-7.

Signal Reference Voltages

GTLREF

CMOS

A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,

BNR#, BPM[5:0]#, BPMb[3:0]#, BPRI#, BR[1:0]#,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#,

DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#,

HIT#, HITM#, LOCK#, MCERR#, RESET#,

REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#,

PWRGOOD, SMI#, STPCLK#, TCK, TDI, TMS, TRST#

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Intel BFCBASE Data Sheet - Page 22

CMOS Asynchronous and Open Drain Asynchronous Signals, 2.8 Test Access Port (TAP) Connection

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