Intel BFCBASE Data Sheet - Page 121

Document Number: 318080-002

121

Features

Details on each of these sections are described below.

Note:

Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not

rely on this model.

7.4.3.1

Header

To maintain backward compatibility, the Header defines the starting address for each

subsequent section of the PIROM. Software should check for the offset before reading

data from a particular section of the ROM.

Example:

Code looking for the cache data of a processor would read offset 05h to find

a value of 25h. 25h is the first address within the 'Cache Data' section of the PIROM.

7.4.3.1.1

DFR: Data Format Revision

This location identifies the data format revision of the PIROM data structure. Writes to

this register have no effect.

78h

8

Processor Feature Flags

[7] = Multi-Core

[6] = Serial Signature

[5] = Electronic Signature Present

[4] = Thermal Sense Device Present

[3] = Reserved

[2] = OEM EEPROM Present

[1] = Core VID Present

[0] = L3 Cache Present

79h

8

Processor Thread and Core

Information

[7:2] = Number of cores

[1:0] = Number of threads per core

7Ah

8

Additional Processor Feature

Flags

[7] = Reserved

[6] = Intel

®

Cache Safe Technology

[5] = Extended Halt State (C1E)

[4] = Intel

®

Virtualization Technology

[3] = Execute Disable

[2] = Intel

®

64

[1] = Thermal Monitor TM2

[0] = Enhanced Intel

®

SpeedStep

®

Technology

7B-7Ch

16

Thermal Adjustment Factors

(Pending)

[15:8] = Measurement Correction Factor

[7:0] = Temperature Target

7D-7Eh

16

Reserved

Reserved

7Fh

8

Checksum

1 byte checksum

Table 7-6.

Processor Information ROM Data Sections (Sheet 3 of 3)

Offset/Section

# of

Bits

Function

Notes

Offset:

00h

Bit

Description

7:0

Data Format Revision

The data format revision is used whenever fields within the PIROM are

redefined. The initial definition will begin at a value of 1. If a field, or bit

assignment within a field, is changed such that software needs to discern

between the old and new definition, then the data format revision field will be

incremented.

00h: Reserved

01h: Initial definition

02h: Second revision

03h: Third revision

04h: Fourth revision

(Defined by this document)

05h-FFh: Reserved

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Intel BFCBASE Data Sheet - Page 121

Header, DFR: Data Format Revision, Table 7-6.

Page 121 highlights