Intel BFCBASE Data Sheet - Page 19

Document Number: 318080-002

19

Electrical Specifications

Notes:

1.

When this VID pattern is observed, the voltage regulator output should be disabled.

2.

Shading denotes the expected VID range of the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel®

Xeon® Processor 7300 Series.

3.

The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see

Section 6.2.3

), Extended HALT state transitions (see

Section 7.2.2

), or Enhanced Intel SpeedStep

®

Technology transitions

(see

Section 7.3

).

The Extended HALT state must be enabled for the processor to remain within its specifications.

4.

Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code is

received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until

power is cycled. Refer to Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design

Guidelines.

Table 2-3.

Voltage Identification Definition

HEX

VID6

400

mV

VID5

200

mV

VID4

100

mV

VID3

50

mV

VID2

25

mV

VID1

12.5

mV

V

CC_MAX

HEX

VID6

400

mV

VID5

200

mV

VID4

100

mV

VID3

50

mV

VID2

25

mV

VID1

12.5

mV

V

CC_MAX

7A

1

1

1

1

0

1

0.8500

3C

0

1

1

1

1

0

1.2375

78

1

1

1

1

0

0

0.8625

3A

0

1

1

1

0

1

1.2500

76

1

1

1

0

1

1

0.8750

38

0

1

1

1

0

0

1.2625

74

1

1

1

0

1

0

0.8875

36

0

1

1

0

1

1

1.2750

72

1

1

1

0

0

1

0.9000

34

0

1

1

0

1

0

1.2875

70

1

1

1

0

0

0

0.9125

32

0

1

1

0

0

1

1.3000

6E

1

1

0

1

1

1

0.9250

30

0

1

1

0

0

0

1.3125

6C

1

1

0

1

1

0

0.9375

2E

0

1

0

1

1

1

1.3250

6A

1

1

0

1

0

1

0.9500

2C

0

1

0

1

1

0

1.3375

68

1

1

0

1

0

0

0.9625

2A

0

1

0

1

0

1

1.3500

66

1

1

0

0

1

1

0.9750

28

0

1

0

1

0

0

1.3625

64

1

1

0

0

1

0

0.9875

26

0

1

0

0

1

1

1.3750

62

1

1

0

0

0

1

1.0000

24

0

1

0

0

1

0

1.3875

60

1

1

0

0

0

0

1.0125

22

0

1

0

0

0

1

1.4000

5E

1

0

1

1

1

1

1.0250

20

0

1

0

0

0

0

1.4125

5C

1

0

1

1

1

0

1.0375

1E

0

0

1

1

1

1

1.4250

5A

1

0

1

1

0

1

1.0500

1C

0

0

1

1

1

0

1.4375

58

1

0

1

1

0

0

1.0625

1A

0

0

1

1

0

1

1.4500

56

1

0

1

0

1

1

1.0750

18

0

0

1

1

0

0

1.4625

54

1

0

1

0

1

0

1.0875

16

0

0

1

0

1

1

1.4750

52

1

0

1

0

0

1

1.1000

14

0

0

1

0

1

0

1.4875

50

1

0

1

0

0

0

1.1125

12

0

0

1

0

0

1

1.5000

4E

1

0

0

1

1

1

1.1250

10

0

0

1

0

0

0

1.5125

4C

1

0

0

1

1

0

1.1375

0E

0

0

0

1

1

1

1.5250

4A

1

0

0

1

0

1

1.1500

0C

0

0

0

1

1

0

1.5375

48

1

0

0

1

0

0

1.1625

0A

0

0

0

1

0

1

1.5500

46

1

0

0

0

1

1

1.1750

08

0

0

0

1

0

0

1.5625

44

1

0

0

0

1

0

1.1875

06

0

0

0

0

1

1

1.5750

42

1

0

0

0

0

1

1.2000

04

0

0

0

0

1

0

1.5875

40

1

0

0

0

0

0

1.2125

02

0

0

0

0

0

1

1.6000

3E

0

1

1

1

1

1

1.2250

00

0

0

0

0

0

0

OFF

1

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	16
2.2.2 VTT Decoupling	16
2.2.3 Front Side Bus AGTL+ Decoupling	16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.3.2 PLL Power Supply	17
2.4 Voltage Identification (VID)	17
2.5 Reserved, Unused, or Test Signals	20
2.6 Front Side Bus Signal Groups	20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	22
2.9 Mixing Processors	23
2.10 Absolute Maximum and Minimum Ratings	23
2.11 Processor DC Specifications	24
2.11.1 Flexible Motherboard Guidelines (FMB)	25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications	35
2.11.3 VCC Overshoot Specification	37
2.11.4 AGTL+ FSB Specifications	38
2.12 Front Side Bus AC Specifications	40
2.13 Processor AC Timing Waveforms	45
3 Mechanical Specifications	57
3.1 Package Mechanical Drawing	57
3.2 Processor Component Keepout Zones	60
3.3 Package Loading Specifications	66
3.4 Package Handling Guidelines	67
3.5 Package Insertion Specifications	67
3.6 Processor Mass Specifications	67
3.7 Processor Materials	67
3.8 Processor Markings	68
3.9 Processor Pin-Out Coordinates	69
4 Pin Listing	71
4.1 Pin Assignments	71
4.1.1 Pin Listing by Pin Name	71
4.1.2 Pin Listing by Pin Number	79
5 Signal Definitions	87
5.1 Signal Definitions.	87
6 Thermal Specifications	95
6.1 Package Thermal Specifications	95
6.1.1 Thermal Specifications	95
6.1.2 Thermal Metrology	102
6.2 Processor Thermal Features	103
6.2.1 Thermal Monitor Features	103
6.2.2 Thermal Monitor	103
6.2.3 Thermal Monitor 2	104
6.2.4 On-Demand Mode	105
6.2.5 PROCHOT# Signal	106
6.2.6 FORCEPR# Signal	106
6.2.7 THERMTRIP# Signal	106
6.3 Platform Environment Control Interface (PECI)	107
6.3.1 Introduction	107
6.3.2 PECI Specifications	108
7 Features	111
7.1 Power-On Configuration Options	111
7.2 Clock Control and Low Power States	111
7.2.1 Normal State	112
7.2.2 HALT or Extended HALT State	112
7.2.3 Stop-Grant State	114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	115
7.3 Enhanced Intel SpeedStep® Technology	115
7.4 System Management Bus (SMBus) Interface	116
7.4.1 SMBus Device Addressing	117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions	118
7.4.3 Processor Information ROM (PIROM)	119
7.4.4 Checksums	137
7.4.5 Scratch EEPROM	137
8 Boxed Processor Specifications	139
8.1 Introduction	139
8.2 Thermal Specifications	139
8.2.1 Boxed Processor Cooling Requirements	139
9 Debug Tools Specifications	141
9.1 Debug Port System Requirements	141
9.2 Logic Analyzer Interface (LAI)	141
9.2.1 Mechanical Considerations	141

Intel BFCBASE Data Sheet - Page 19

Table 2-3., Voltage Identification Definition

Page 19 highlights