Intel BFCBASE Data Sheet - Page 42

Electrical Specifications Table 2-22. Miscellaneous GTL+ AC Specifications T# Parameter T35: Asynchronous GTL+ input pulse width T36: PWRGOOD assertion to RESET# de-assertion T37: BCLK stable to PWRGOOD assertion T38: PROCHOT# pulse width T39: THERMTRIP# assertion until VCC removed T40: FERR# valid delay from STPCLK# deassertion T41: VCC stable to PWRGOOD assertion T42: PWRGOOD rise time T43: VCC_BOOT stable to VID / BSEL valid T44: VID / BSEL valid to VCC stable T48: VTT stable to VID / BSEL valid T49: VCCPLL stable to PWRGOOD assertion Min 30 1 10 500 0 0.05 10 100 10 1 Max 10 500 5 500 20 Unit ns ms BCLKs µs ms BCLKs ms ns µs µs µs ms Figure 2-24 2-24 2-20 2-21 2-25 2-24 2-24 2-24 2-24 2-24 Notes 1, 2, 3, 4 5 6,12 7 8 10 11 9,10 10 10 10 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage (VCROSS). PWRGOOD is referenced to BCLK0 rising edge at 0.5 * VTT. 3. These signals may be driven asynchronously. 4. Refer to Section 7.2 for additional timing requirements for entering and leaving low power states. 5. A minimum pulse width of 500 µs is recommended when FORCEPR# is asserted by the system 6. Refer to the PWRGOOD signal definition in Section 5 for more details information on behavior of the signal. 7. Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion and before the deassertion of PROCHOT# for the processor to enable or disable the TCC. 8. Intel recommends the VTT power supply also be removed upon assertion of THERMTRIP#. 9. This specification requires that the VID and BSEL signals be sampled no earlier than 10 μs after VCC (at VCC_BOOT voltage) and VTT are stable. 10. Parameter must be measured after applicable voltage level is stable. "Stable" means that the power supply is in regulation as defined by the minimum and maximum DC/AC specifications for all components being powered by it. 11. The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor. Measured between (0.3* VTT) and (0.7*VTT). 12. See Table 2-19 for BCLK specifications. Table 2-23. Front Side Bus AC Specifications (Reset Conditions) T# Parameter T45: Reset Configuration Signals (A[39:3]#, BR[1:0]#, INIT#, SMI#) Setup Time T46: Reset Configuration Signals (A[39:3]#, INIT#, SMI#) Hold Time T47: Reset Configuration Signals BR[1:0]# Hold Time Min 480 2 2 Max 20 2 Unit µs Figure 2-24 BCLKs 2-24 BCLKs 2-24 Notes 1 2 2 Notes: 1. Before the clock that de-asserts RESET# 2. After the clock that de-asserts RESET#. Table 2-24. TAP Signal Group AC Specifications (Sheet 1 of 2) T# Parameter Min Max T55: TCK Period 30 T56: TDI, TMS Setup Time 7.5 Unit ns ns Figure 2-12 2-19 Notes 1, 2, 8 3 4,7 42 Document Number: 318080-002